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Design Team Project: Physical Design ( Layout ) Kyungseok Kim ELEC 7770 Advanced VLSI Design Lecturer: Dr. Vishwani D. Agrawal.

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Presentation on theme: "Design Team Project: Physical Design ( Layout ) Kyungseok Kim ELEC 7770 Advanced VLSI Design Lecturer: Dr. Vishwani D. Agrawal."— Presentation transcript:

1 Design Team Project: Physical Design ( Layout ) Kyungseok Kim ELEC 7770 Advanced VLSI Design Lecturer: Dr. Vishwani D. Agrawal

2 Outline ASIC Design Flow ASIC Design Flow Physical Design: Automated IC Layout Physical Design: Automated IC Layout Design Objects: CPU, MUX (Alternative) Design Objects: CPU, MUX (Alternative) Conclusion Conclusion Reference Reference

3 ASIC Design Flow Behavioral Model VHDL/Verilog Gate-Level Netlist Transistor-Level Netlist Physical Layout Map/Place/Route DFT/BIST & ATPG Verify Behavior Verify Function Verify Function & Timing Verify Function & Timing DRC & LVS Verification IC Mask Data Standard Cell IC & FPGA/CPLD Synthesis Test vectors Full-custom IC Simulation

4 Layout Procedure: CPU Foorplanning Total Area = 157284512.0 um 2 Number of internal rows = 55 Avg. instance height = 120.0 um Avg. channel height = 120.0 um Total connections (pins - nets) = 44099 Internal zone width = 12008.0 um Internal zone height = 13204.0 um Aspect ratio = 0.93 CPU Schematic Symbol -TSMC 018um Tech.

5 Placing Std. CellsConnecting Ports Bipartition for Placement Number of core instances = 7601 Number of signal nets = 8987 Number of power nets = 2

6 Auto Routing Overflows Try another option for reducing overflows, but couldn’t remove all overflows!!! Check Shorts: OK Num of Overflows = 6678 Number of global routing nodes: 157444 Number of global routing arcs : 201136 Changing Options In Auto Route

7 Automated Layout Flow Layout: MUX 1. 3. 2. 5. 4. 6. MUX Gate Level Complete Layout DRC OK!LVS OK! Extraction: Lumped R&C, Coupled C Post Simulation: Timing, Power

8 Conclusion Automated Layout not Perfect!!! Automated Layout not Perfect!!! - Overflows, Shorts, Dependent on Synthesis & Options in Floorplan and Route Need communication in Synthesis Step Need communication in Synthesis Step - Reduce Overheads in Area and Net congestions Post-layout Simulation for the Spec. Post-layout Simulation for the Spec. For Fabrication, Add Pads and Power For Fabrication, Add Pads and Power Generate GDS II Generate GDS II

9 Reference Dr. Nelson’s Lecture notes in ELEC6250 Dr. Nelson’s Lecture notes in ELEC6250 Mentor IC Station User Manual Mentor IC Station User Manual Mentor ADK Tutorial Mentor ADK Tutorial THANK YOU !!

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