1. Digital Design – Programmable Processors Chapter 8 - Programmable Processors

2. 2 Digital Design Programmable Processors Figure 8.1 Basic datapath of a programmable processor.

3. 3 Digital Design Programmable Processors Figure 8.2 Basic datapath operations: load (left), ALU operation (center), and store (right).

4. 4 Digital Design Programmable Processors Figure 8.3 The control unit in a programmable processor.

5. 5 Digital Design Programmable Processors Figure 8.4 Basic controller states.

6. 6 Digital Design Programmable Processors Figure 8.5 A program that computes D[9]=D[0]+D[1], using a given instruction set.

7. 7 Digital Design Programmable Processors Figure 8.6 High-level state machine description of a three-instruction programmable processor.

8. 8 Digital Design Programmable Processors Figure 8.7 Refined datapath and control unit for the three-instruction processor.

9. 9 Digital Design Programmable Processors Figure 8.8 FSM for the three-instruction processor’s controller.

10. 10 Digital Design Programmable Processors Figure 8.1 Six-instruction instruction set.

11. 11 Digital Design Programmable Processors Figure 8.9 Control unit and datapath for the six-instruction processor.

12. 12 Digital Design Programmable Processors Figure 8.10 Controller’s FSM for the six-instruction processor.

13. 13 Digital Design Programmable Processors Table 8.2 Instruction opcodes.

14. 14 Digital Design Programmable Processors Figure 8.11 Assembly code (left) and machine code (right) for a sample program.