VHDL Rabee Shatnawi & Rami Haddad. What is this presentation about?! This presentation will introduce the key concepts in VHDL and the important syntax.

VHDL Rabee Shatnawi & Rami Haddad

What is this presentation about?! This presentation will introduce the key concepts in VHDL and the important syntax required for most VHDL designs,

Why to use VHDL? In most cases, the decision to use VHDL over other languages such as Verilog or SystemC, will have less to do with designer choice, and more to do with software availability and company decisions…. Or the professor's choice ;-) ;-)

Verilog has come from a ‘bottom-up’ tradition and has been heavily used by the IC industry for cell-based design, whereas the VHDL language has been developed much more from a ‘topdown’ perspective. Of course, these are generalizations and largely out of date in a modern context

Entity: model interface The entity defines how a design element described in VHDL connects to other VHDL models … and also defines the name of the model. It allows the definition of any parameters that are to be passed into the model using hierarchy.

Entity definition entity test is …. end entity test; or: entity test is … end test;

Ports How to connect Entities together? How to connect Entities together? -The method of connecting entities together is using PORTS. - - PORTS are defined in the entity using the following method: port (...list of port declarations... );

The port declaration defines the type of connection and direction where appropriate. port ( in1, in2 : in bit; out1 : out bit );

Entity Port Modes in: in: –signal values are read-only out: out: –signal values are write-only buffer: buffer: –comparable to out –signal values may be read, as well inout: inout: – bidirectional port

Generics If the model has a parameter, then it is defined using generics. generic ( gain : integer := 4; time_delay : time = 10 ns );

Constants It is also possible to include model specific constants in the entity using the standard declaration of constants method constant : rpullup : real := 1000.0;

a complete examples, meet our first Entity……. test entity test is port ( in1, in2 : in bit; out1 : out bit ); generic ( gain : integer := 4; time_delay : time := 10 ns ); constant : rpullup : real := 1000.0; end entity test;

Architecture: model behavior Implementation of the design Implementation of the design Always connected with a specific entity Always connected with a specific entity –one entity can have several architectures –entity ports are available as signals within the architecture Contains concurrent statements Contains concurrent statements

Basic definition of an architecture While the entity describes the interface and parameter aspects of the model ………. the architecture defines the behavior.

There are several types of VHDL architecture and …. VHDL allows different architectures to be defined for the same entity. architecture behaviour of test is..architecture declarations begin...architecture contents end behaviour; any local signals or variables can be declared here

Signals Signals are the primary objects describing the hardware system and are equivalent to “wires”. Signals are the primary objects describing the hardware system and are equivalent to “wires”. They represent communication channels among concurrent statements of system application. They represent communication channels among concurrent statements of system application. Signals can be declared in: Signals can be declared in: –Package declaration –Architecture –Block: –Subprograms:

Hierarchical design Functions Packages Components Procedures

Functions A simple way of encapsulating behavior in a model that can be reused in multiple architectures. Can be defined locally to an architecture or more commonly in a package

The simple form of a function is to define a header with the input and output variables as shown below: function name ( input declarations ) return output _ type is... variable declarations begin... function body end

function mult (a,b : integer) return integer is begin return a * b; end;

Package : Function containers package name is...package header contents end package; package body name is... package body contents end package body; The header: is the place where the types and functions are declared package body: where the declarations themselves take place

Component

library ieee; use ieee.std_logic_1164.all; -- here is the entity entity halfadd is port (a, b : in std_logic; sum, c : out std_logic); end halfadd; architecture comp of halfadd is begin -- a concurrent statement implementing the and gate c <= a and b; -- a concurrent statement implementing the xor gate sum <= a xor b; end comp;

library ieee; use ieee.std_logic_1164.all; entity fulladd is port (ina, inb, inc : in std_logic; sumout, outc : out std_logic); end fulladd; architecture top of fulladd is component halfadd port (a, b : in std_logic; sum, c : out std_logic); end component; signal s1, s2, s3 : std_logic; begin -- a structural instantiation of two half adders h1: halfadd port map( a => ina, b => inb, sum => s1, c => s3); h2: halfadd port map( a => s1, b => inc, sum => sumout, c => s2); outc <= s2 or s3; end top;

VHDL Case insensitive Case insensitive Comments: '--' until end of line Statements are terminated by ';' (may span multiple lines) Comments: '--' until end of line Statements are terminated by ';' (may span multiple lines) List delimiter: ',' List delimiter: ',' Signal assignment: '<=‘ Signal assignment: '<=‘ User defined names: User defined names: –letters, numbers, underscores –start with a letter

VHDL …. Identifier (Normal) Identifier Letters, numerals, underscores (Normal) Identifier Letters, numerals, underscores Case insensitive Case insensitive No two consecutive underscores No two consecutive underscores Must begin with a letter Must begin with a letter Not a VHDL keyword Not a VHDL keyword mySignal_23 -- normal identifier rdy, RDY, Rdy -- identical identifiers vector_&_vector -- X : special character last of Zout -- X : white spaces idle__state -- X : consecutive underscores 24th_signal -- X : begins with a numeral open, register -- X : VHDL keywords

VHDL Structural Elements Entity : Interface Architecture : Entity : Interface Architecture : Implementation, behavior, function Implementation, behavior, function Configuration : Model chaining, structure, hierarchy Configuration : Model chaining, structure, hierarchy Process : Concurrency, event controlled Process : Concurrency, event controlled Package : Modular design, standard solution, Package : Modular design, standard solution, data types, constants data types, constants Library : Compilation, object code Library : Compilation, object code

Hierarchical Model Layout VHDL allows for a hierarchical model layout, which means that a module can be assembled out of several submodules. The connections between these submodules are defined within the architecture of a top module. As you can see, a fulladder can be built with the help of two halfadders (module1, module2) and an OR gate (module3). VHDL allows for a hierarchical model layout, which means that a module can be assembled out of several submodules. The connections between these submodules are defined within the architecture of a top module. As you can see, a fulladder can be built with the help of two halfadders (module1, module2) and an OR gate (module3).

entity FULLADDER is port (A,B, CARRY_IN: in bit; SUM, CARRY: out bit); end FULLADDER; architecture STRUCT of FULLADDER is signal W_SUM, W_CARRY1, W_CARRY2 : bit; component HALFADDER port (A, B : in bit; SUM, CARRY : out bit); end component; component ORGATE port (A, B : in bit; RES : out bit); end component; begin begin MODULE1: HALFADDER port map( A, B, W_SUM, W_CARRY1 ); MODULE2: HALFADDER port map ( W_SUM, CARRY_IN, SUM, W_CARRY2 ); MODULE3: ORGATE port map ( W_CARRY2, W_CARRY1, CARRY ); end STRUCT; Component :example ENTITY half_adder IS PORT ( A, B : IN STD_LOGIC; sum, carry : OUT STD_LOGIC ); END half_adder; ARCHITECTURE structural OF half_adder IS COMPONENT xor2 PORT ( a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END COMPONENT; COMPONENT and2 PORT ( a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END COMPONENT; BEGIN ex1 : xor2 PORT MAP ( a => a, b => b, c => sum ); or1 : and2 PORT MAP ( a => a, b => b, c => carry ); END structural; ENTITY and2 IS PORT ( a, b : IN STD_LOGIC; output : OUT STD_LOGIC ); END and2; ARCHITECTURE gate OF and2 IS BEGIN output <= ( a AND b ) AFTER 5ns; END gate begin MODULE1: HALFADDER port map ( A => A, SUM => W_SUM, B => B, CARRY => W_CARRY 1 );... end STRUCT;

Process The process in VHDL is the mechanism by which sequential statements can be executed in the correct sequence, and with more than one process, concurrently. –Contains sequentially executed statements –Exist within an architecture, –only Several processes run concurrently –Execution is controlled either via sensitivity list (contains trigger signals), or wait-statements

Process JustToShow: process Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; wait ; end process JustToShow; JustToShow: process Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; Some statement 5; end process JustToShow; Wait for type expression Wait until condition Wait on sensitivity list Complex wait Complex wait Wait until CLK=‘1’ Wait on Enable Wait unit date after 10ns Wait for 10ns

Process JustToShow: process ( ) Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; end process JustToShow; VHDL provides a construct called sensenitivity list of a process VHDL provides a construct called sensenitivity list of a process The list specified next to the process keyword. The list specified next to the process keyword. The same as wait on sensitivity_list at the end of a process The same as wait on sensitivity_list at the end of a process JustToShow: process Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; wait on end process JustToShow; SomeSig

Process JustToShow: process (signa1,signal2,signal3) Begin Some statement 1; Some statement 2; Some statement 3; Some statement 4; Some statement 5; end process JustToShow; Signal2 has changed Signal3 has changed

Example: JustToShow: process (signal1,signal2,signal3) Begin Some statement 1; signal3<=signal1+5; Some statement 3; Some statement 4; Some statement 5; end process JustToShow Signa1= 0 Signal3=5 6

Example: process(C,D)beginA<=2;B<=A+C;A<=D+1;E<=A*2; end process; A=1 B=1 C=1 D=1 E=1 A<=2 B<=A+C; A<=D+1 E<=A*2 ; 3 2 2

Variables Variables are available within processes Variables are available within processes –Named within process declarations –Known only in this process Immediate assignment Immediate assignment An assignment to a variable is made with := symbol. An assignment to a variable is made with := symbol. The assignment take instance effect and each variable can be assigned new values as many times as needed. The assignment take instance effect and each variable can be assigned new values as many times as needed. A variable declaration look similar to a signal declaration and starts with variable keyword A variable declaration look similar to a signal declaration and starts with variable keyword Keep the last value Keep the last value Possible assignments Possible assignments –Signal to variable –Variable to signal –Types have to match

Variables vs. Signals Signals Signals –In a process, only the last signal assignment is carried out –Assigned when the process execution is suspended –“ <= “ to indicate signal assignment Variables Variables –Assigned immediately –The last value is kept –“ := “ to indicate variable assignment

Variables vs. Signals (contd.) signal A, B, C, X, Y : integer; begin process (A, B, C) variable M, N : integer; begin M := A; N := B; X <= M + N; M := C; Y <= M + N; end process; signal A, B, C, Y, Z : integer; signal M, N : integer; begin process (A, B, C, M, N) begin M <= A; N <= B; X <= M + N; M <= C; Y <= M + N; end process; end process; + A B X + C B Y + C B X + C B Y

Variables process(C,D) Variable Av,Bv,Ev :integer :=0; beginA<=2;Bv<=Av+C;Av<=D+1; Ev <= Av*2; A <=Av; B <=Bv; E <=Ev; end process

The world is not sequential Its convention to specify things in a sequential way, this is not the simplest way to describe reality. Its convention to specify things in a sequential way, this is not the simplest way to describe reality. Processes are concurrent statements Processes are concurrent statements Several processes run parallel linked by signals in the sensitivity list Several processes run parallel linked by signals in the sensitivity list sequential execution of statements sequential execution of statements Link to processes of other entity/architecture pairs via entity interface Link to processes of other entity/architecture pairs via entity interface

Architecture SomeArch of SomeEnt is BeginP1:process(A,B,E)BeginSomestatment;Somestatment;Somestatment;D<=Someexpression;; End process P1; P2:process(A,C) Begin Somestatment; End process P1; P3:process(B,D) Begin Somestatment; End process P1; end Architecture SomeArch ;

IF Statement: entity IF_STATEMENT is port (A, B, C, X : in bit_vector (3 downto 0); Z : out bit_vector (3 downto 0); end IF_STATEMENT; architecture EXAMPLE1 of IF_STATEMENT is begin process (A, B, C, X) begin Z "1000") then Z "1000") then Z <= C; end if; end process; end EXAMPLE1; architecture EXAMPLE2 of IF_STATEMENT is begin process (A, B, C, X) begin if (X = "1111") then Z "1000") then Z "1000") then Z <= C; else Z <= a; end if; end process; end EXAMPLE2;

entity RANGE_1 is port (A, B, C, X : in integer range 0 to 15; Z : out integer range 0 to 15; end RANGE_1; architecture EXAMPLE of RANGE_1 is begin process (A, B, C, X) begin case X is when 0 => Z Z Z Z Z Z Z Z <= 0; end case; end process; end EXAMPLE; entity RANGE_2 is port (A, B, C, X : in bit_vector(3 downto 0); Z : out bit_vector(3 downto 0); end RANGE_2; architecture EXAMPLE of RANGE_2 is begin process (A, B, C, X) begin case X is when "0000" => Z Z -- wrong Z Z Z Z -- wrong Z Z <= 0; end case; end process; end EXAMPLE; Case statement

For loop entity FOR_LOOP is port (A : in integer range 0 to 3; Z : out bit_vector (3 downto 0)); end FOR_LOOP; architecture EXAMPLE of FOR_LOOP is begin process (A) begin Z <= "0000"; for I in 0 to 3 loop if (A = I) then Z(I) <= `1`; end if; end loop; end process; end EXAMPLE; entity FOR_LOOP is port (A : in integer range 0 to 3; Z : out bit_vector (3 downto 0)); end FOR_LOOP; architecture EXAMPLE of FOR_LOOP is begin process (A) begin Z <= "0000"; for I in 0 to 3 loop if (A = I) then Z(I) <= `1`; end if; end loop; end process; end EXAMPLE;

entity CONV_INT is port (VECTOR: in bit_vector(7 downto 0); RESULT: out integer); end CONV_INT; architecture A of CONV_INT is begin process(VECTOR) variable TMP: integer; begin TMP := 0; for I in 7 downto 0 loop if (VECTOR(I)='1') then TMP := TMP + 2**I; end if; end loop; RESULT <= TMP; end process; end A; architecture B of CONV_INT is begin process(VECTOR) variable TMP: integer; begin TMP := 0; for I in VECTOR'range loop if (VECTOR(I)='1') then TMP := TMP + 2**I; end if; end loop; RESULT <= TMP; end process; end B; architecture C of CONV_INT is begin process(VECTOR) variable TMP: integer; variable I : integer; begin TMP := 0; I := VECTOR'high; while (I >= VECTOR'low) loop if (VECTOR(I)='1') then TMP := TMP + 2**I; end if; I := I - 1; end loop; RESULT = VECTOR'low) loop if (VECTOR(I)='1') then TMP := TMP + 2**I; end if; I := I - 1; end loop; RESULT <= TMP; end process; end C;

Exit & Next The exit command allows a FOR loop to be exited completely. This can be useful when a condition is reached and the remainder of the loop is no longer required. The syntax for the exit command is shown below: for i in 0 to 7 loop if ( i = 4 ) then exit; endif; endloop; The next command allows a FOR loop iteration to be exited, this is slightly different to the exit command in that the current iteration is exited, but the overall loop continues onto the next iteration. This can be useful when a condition is reached and the remainder of the iteration is no longer required. An example for the next command is shown below: for i in 0 to 7 loop if ( i = 4 ) then next; endif; endloop;

Conditional Signal Assignment entity CONDITIONAL_ASSIGNMENT is port (A, B, C, X : in bit_vector (3 downto 0); Z_CONC : out bit_vector (3 downto 0); Z_SEQ : out bit_vector (3 downto 0)); end CONDITIONAL_ASSIGNMENT; architecture EXAMPLE of CONDITIONAL_ASSIGNMENT is begin -- Concurrent version of conditional signal assignment Z_CONC "1000" else A; -- Equivalent sequential statements process (A, B, C, X) begin if (X = "1111") then Z_SEQ "1000") then Z_SEQ "1000" else A; -- Equivalent sequential statements process (A, B, C, X) begin if (X = "1111") then Z_SEQ "1000") then Z_SEQ <= C; else Z_SEQ <= A; end if; end process; end EXAMPLE; TARGET <= VALUE; TARGET <= VALUE_1 when CONDITION_1 else VALUE_2 when CONDITION_2 else... VALUE_n;

Selected Signal Assignment entity SELECTED_ASSIGNMENT is port (A, B, C, X : in integer range 0 to 15; Z_CONC : out integer range 0 to 15; Z_SEQ : out integer range 0 to 15); end SELECTED_ASSIGNMENT; architecture EXAMPLE of SELECTED_ASSIGNMENT is begin entity SELECTED_ASSIGNMENT is port (A, B, C, X : in integer range 0 to 15; Z_CONC : out integer range 0 to 15; Z_SEQ : out integer range 0 to 15); end SELECTED_ASSIGNMENT; architecture EXAMPLE of SELECTED_ASSIGNMENT is begin -- Concurrent version of selected signal assignment with X select Z_CONC Z_SEQ Z_SEQ Z_SEQ Z_SEQ Z_SEQ Z_SEQ Z_SEQ Z_SEQ <= 0; end process; end EXAMPLE; with EXPRESSION select TARGET <= VALUE_1 when CHOICE_1, VALUE_2 when CHOICE_2 | CHOICE_3, VALUE_3 when CHOICE_4 to CHOICE_5, · · · VALUE_n when others;

Miscellanies operators **absnot Multiplying operators * / Modrem Signed operator +- Adding operator +-& Shift operator sllsrlslasra rolror Relational operation =/=<<= >>= Logical operator andornand norxorxnorOperators

Subprograms Functions Functions – function name can be an operator –arbitrary number of input parameters –exactly one return value –no WAIT statement allowed –function call VHDL expression Procedures Procedures – arbitrary number of parameters of any possible direction (input/output/inout) –RETURN statement optional (no return value!) –procedure call VHDL statement Subprograms can be overloaded Subprograms can be overloaded Parameters can be constants, signals, variables or files Parameters can be constants, signals, variables or files

function architecture EXAMPLE of FUNCTIONS is function COUNT_ZEROS (A : bit_vector) return integer is variable ZEROS : integer; begin ZEROS := 0; for I in A'range loop if A(I) = '0' then ZEROS := ZEROS +1; end if; end loop; return ZEROS; end COUNT_ZEROS; signal WORD: bit_vector(15 downto 0); signal WORD_0: integer; signal IS_0: boolean; architecture EXAMPLE of FUNCTIONS is function COUNT_ZEROS (A : bit_vector) return integer is variable ZEROS : integer; begin ZEROS := 0; for I in A'range loop if A(I) = '0' then ZEROS := ZEROS +1; end if; end loop; return ZEROS; end COUNT_ZEROS; signal WORD: bit_vector(15 downto 0); signal WORD_0: integer; signal IS_0: boolean; begin WORD_0 0 then IS_0 0 then IS_0 <= false; end if; wait; end process; end EXAMPLE;

procedure architecture EXAMPLE of PROCEDURES is procedure COUNT_ZEROS (A: in bit_vector;signal Q: out integer) is variable ZEROS : integer; begin ZEROS := 0; for I in A'range loop if A(I) = '0' then ZEROS := ZEROS +1; end if; end loop; Q <= ZEROS; architecture EXAMPLE of PROCEDURES is procedure COUNT_ZEROS (A: in bit_vector;signal Q: out integer) is variable ZEROS : integer; begin ZEROS := 0; for I in A'range loop if A(I) = '0' then ZEROS := ZEROS +1; end if; end loop; Q <= ZEROS; end COUNT_ZEROS; signal COUNT: integer; signal IS_0: boolean; begin process begin IS_0 0 then IS_0 0 then IS_0 <= false; end if; wait; end process; end EXAMPLE;

Data Types Each object in VHDL has to be of some type, which defines possible values and operations that can be performed on this object (and other object of the same type). Each object in VHDL has to be of some type, which defines possible values and operations that can be performed on this object (and other object of the same type). VHDL is strongly typed language which causes that two types defined in exactly the same way but differing only by names will be considered differently. VHDL is strongly typed language which causes that two types defined in exactly the same way but differing only by names will be considered differently. If a translation from one type to another is required, then type convention must be applied even if the two types are similar. If a translation from one type to another is required, then type convention must be applied even if the two types are similar.

A physical type is a numeric type for representing some physical quantity, such as mass, length, time or voltage. type distance is range 0 to 1E5 units um; mm = 1000 um; In_a=25400 um; end units; Variable Dis1,dis2 :Distance; Dis1:=28mm; An integer type is a scalar whose set of values include integer numbers in specific range. type byte_int is range 0 to 255; type voltage_level is range 0 to 5; A floating point type is a discrete approximation to the set of real numbers in a specified range. type signal_level is range –10.00 to +10.00; An enumeration type is a type whose values are defined by listing (enumerating) them explicitly. type logic_level is (unknown, low, undriven, high); Data Types type Scalar type Integer type Floating point Enormous type Physical type Composite type Array record Access type file

Data Types type Scalar type Integer type Floating point Enormous type Physical type Composite type Array record Access type file Is an indexed collection of elements all of the same type. Arrays may be one- dimensional (with one index) or multidimensional (with a number of indices). type VAR is array (0 to 7) of integer; constant SETTING: VAR := (2,4,6,8,10,12,14,16); type VECTOR2 is array (natural range <>, natural range <>) of std_logic; variable ARRAY3x2: VECTOR2 (1 to 3, 1 to 2)) := ((‘1’,’0’), (‘0’,’-‘), (1, ‘Z’)); A record type allows declaring composite objects whose elements can be from different types. Type RegName is (AX,BX,DX); Type Operation is record Mnemonic:string (1 to 10); OpCode:Bit_Vector(3 downto 0); Op1,op2,Reg:RegName; End record; Variable Instr3:= Operation; Instr3. Mnemonic:= “Mul AX, BX”; Inst3.Op1:=Ax;

Subtype A type with a constraints. A value belong to a subtype of a given type if it belongs to the type and satisfied the constraints. A type with a constraints. A value belong to a subtype of a given type if it belongs to the type and satisfied the constraints. –Subtype Digits is Integer range 0 to 9; Integer is a predefined type and the subtype digits will constraints the type to ten values only. Integer is a predefined type and the subtype digits will constraints the type to ten values only.

Standard Data Types Every type has a number of possible values Every type has a number of possible values Standard types are defined by the language Standard types are defined by the language User can define his own types User can define his own types package STANDARD is type BOOLEAN is (FALSE,TRUE); type BIT is (`0`,`1`); type CHARACTER is (-- ascii set); type INTEGER is range -- implementation_defined type REAL is range -- implementation_defined -- BIT_VECTOR, STRING, TIME end STANDARD;

Alias Signal Instruction :Bit_vector( 15 downto 0 ); Signal Instruction :Bit_vector( 15 downto 0 ); –Alias OpCode : Bit_vector( 3 downto 0 ) is Instruction ( 15 downto 12 ); –Alias Source : Bit_vector( 1 downto 0 ) is Instruction ( 11 downto 10 ); –Alias design : Bit_vector( 1 downto 0 ) is Instruction ( 9 downto 8 ); –Alias Immdata : Bit_vector( 7 downto 0 ) is Instruction ( 7 downto 0 );

Aggregate A basic operation that combines one or more values into a composite value of a record or array type; A basic operation that combines one or more values into a composite value of a record or array type; –Variable data_1 :Bit_vecot(0 to 3) := (‘0’,’1’,’0’,’1’); –Variable data_1 :Bit_vecot(0 to 3) := (1=>‘1’,0=>’0’, 3=>’1’,2=>’0’); –Signal data_Bus :std_logic_vector (15 downto 0) data_Bus ‘0’, 7 downto 0 =>’1’); –Signal data_Bus :std_logic_vector (15 downto 0) data_Bus ‘0’, others=>’1’); –Signal data_Bus :std_logic_vector (15 downto 0) data_Bus<=(others=>’z’’); –Type Status_record is record Code:Integer; Code:Integer; Name:string(1 to 4); Name:string(1 to 4); End record; End record; Variable Status_var: Status_record :=(code=>57, name=>”MOVE”); Variable Status_var: Status_record :=(code=>57, name=>”MOVE”);

Concatenation architecture EXAMPLE_1 of CONCATENATION is signal BYTE : bit_vector (7 downto 0); signal A_BUS, B_BUS : bit_vector (3 downto 0); begin BYTE <= A_BUS & B_BUS; end EXAMPLE; architecture EXAMPLE_1 of CONCATENATION is signal BYTE : bit_vector (7 downto 0); signal A_BUS, B_BUS : bit_vector (3 downto 0); begin BYTE <= A_BUS & B_BUS; end EXAMPLE; Variable Bytedat : bit_vector(7 downto 0); Variable Bytedat : bit_vector(7 downto 0); Alias Modulus: bit_vector(6 downto 0) is bytedat(6 downto 0); …… Bytedate:=‘1’ & modulas;

Attribute Attributes are a feature of VHDL that allow you to extract additional information about an object (such as a signal, variable or type) that may not be directly related to the value that the object carries. Attributes are a feature of VHDL that allow you to extract additional information about an object (such as a signal, variable or type) that may not be directly related to the value that the object carries. –Type table is array (1 to 8) of Bit; Variable array_1: table:=‘00001111’; Arrat_1’left, the leftmost value of table array is equal to 1; –architecture example of enums is type state_type is (Init, Hold, Strobe, Read, Idle); type state_type is (Init, Hold, Strobe, Read, Idle); signal L, R: state_type; signal L, R: state_type;begin L <= state_type’left; -- L has the value of Init L <= state_type’left; -- L has the value of Init R <= state_type’right; -- R has the value of Idle R <= state_type’right; -- R has the value of Idle end example; – (clock'EVENT and clock='1') –type state_type is (Init, Hold, Strobe, Read, Idle); variable P: integer := state_type’pos(Read); -- P has the value of 3 variable P: integer := state_type’pos(Read); -- P has the value of 3 – type state_type is (Init, Hold, Strobe, Read, Idle); variable V: state_type := state_type’val(2); -- V has the value of Strobe variable V: state_type := state_type’val(2); -- V has the value of Strobe

Reference http://www.seas.upenn.edu/~ese201/vhdl/v hdl_primer.html#_Toc526061356 http://www.seas.upenn.edu/~ese201/vhdl/v hdl_primer.html#_Toc526061356 http://www.seas.upenn.edu/~ese201/vhdl/v hdl_primer.html#_Toc526061356 http://www.seas.upenn.edu/~ese201/vhdl/v hdl_primer.html#_Toc526061356 http://www.vhdl-online.de/~vhdl/tutorial/ http://www.vhdl-online.de/~vhdl/tutorial/ http://www.vhdl-online.de/~vhdl/tutorial/ http://tams-www.informatik.unihamburg.de /vhdl/doc/cookbook/VHDL Cookbook.pdf http://tams-www.informatik.unihamburg.de /vhdl/doc/cookbook/VHDL Cookbook.pdf http://tams-www.informatik.unihamburg.de /vhdl/doc/cookbook/VHDL Cookbook.pdf http://tams-www.informatik.unihamburg.de /vhdl/doc/cookbook/VHDL Cookbook.pdf

VHDL Rabee Shatnawi & Rami Haddad. What is this presentation about?! This presentation will introduce the key concepts in VHDL and the important syntax.

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VHDL Rabee Shatnawi & Rami Haddad. What is this presentation about?! This presentation will introduce the key concepts in VHDL and the important syntax.

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