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December 1, 2005 ELEC 6970 - Project Presentation 1 Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji.

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Presentation on theme: "December 1, 2005 ELEC 6970 - Project Presentation 1 Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji."— Presentation transcript:

1 December 1, 2005 ELEC 6970 - Project Presentation 1 Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji Ramkumar

2 December 1, 2005ELEC 6970 - Project Presentation2 Problem Statement To Use a dual-supply voltage in order to reduce the power consumption of the 32 x 32 bit integer array multiplier circuit without compromising the overall delay To Use a dual-supply voltage in order to reduce the power consumption of the 32 x 32 bit integer array multiplier circuit without compromising the overall delay

3 December 1, 2005ELEC 6970 - Project Presentation3 Power and Delay Power → Power → V DD 2 Delay → Delay → KV DD ─────── (V DD – V t ) α

4 December 1, 2005ELEC 6970 - Project Presentation4 Approach  Low Voltage Assignment to as many cells as possible  The interconnections in this multiplier circuit makes it difficult  Therefore assign Low Voltage Supply to as many gates as possible

5 December 1, 2005ELEC 6970 - Project Presentation5 Things to watch  Reducing the Voltage Supply will increase the delay of a gate  Therefore assign Low-Voltage Supply only to the gates which do not have any influence on the Critical Path Delay directly or indirectly  Low voltage gate should have adequate voltage swing in order to drive a High Voltage gate its feeding in to.

6 December 1, 2005ELEC 6970 - Project Presentation6 4 x 4 Multiplier

7 December 1, 2005ELEC 6970 - Project Presentation7 Multiplier Cell

8 December 1, 2005ELEC 6970 - Project Presentation8 Low-Voltage Supply Assignment Output Cells along the edge N-1G4 First Row 3(N-1)G1,G2,G3 Second Row to Last Row N(N-1)G1 Left Column 2(N-1)G2,G3

9 December 1, 2005ELEC 6970 - Project Presentation9  Total Number of gates = 6N 2  Number of gates with Low Voltage assignment = (N-1)(N+6) assignment = (N-1)(N+6)  Percentage of the circuit with Reduced V DD =(N-1)(N+6) / 6N 2

10 December 1, 2005ELEC 6970 - Project Presentation10 Percentage of the Circuit with Reduced Voltage Supply

11 December 1, 2005ELEC 6970 - Project Presentation11 Experimental Results for a Cell Voltage (Volts) P dyn (Microwatts) P static (Picowatts) Delay(Sec) 1.89.1246 251 p 1.55.27171 358 p 1.22.87112 537 p 0.90.7967 1.14 n

12 December 1, 2005ELEC 6970 - Project Presentation12 Experimental Results for a 4 x 4 Multiplier Voltage (Volts) P dyn (Microwatts) P static (Nanowatts) Delay(Sec) 1.82131.6 1.57 n 1.5132.11.13 1.76 n 1.275.80.75 1.97 n 0.936.40.46 2.2 n

13 December 1, 2005ELEC 6970 - Project Presentation13 A Single Inverter Voltage (Volts) P dyn (Microwatts) P static (Picowatts) Delay(Sec) 1.81.8810 82 p 1.50.5887 91 p 1.20.1144.6 108 p 0.90.0472.8 236 p

14 December 1, 2005ELEC 6970 - Project Presentation14 4 x 4 bit array Multiplier  N=4   Total Number of Gates = 6N 2 = 6(16) = 96  Number of Gates with Low V DD = (N-1)(N+6) = (3)(10) = 30 = 31.25 % = (3)(10) = 30 = 31.25 %  Number of Gates with Normal V DD = 96 – 30 = 66 = 68.75% 96 – 30 = 66 = 68.75%

15 December 1, 2005ELEC 6970 - Project Presentation15 Power Estimation  Using Dual-Voltages, 1.8V & 1.5V Power Consumption = (0.3125)(132.1uW) + (0.6875)(213uW) = 187.73 uW  12% Power Reduction

16 December 1, 2005ELEC 6970 - Project Presentation16 Power Estimation  Using Dual-Voltages, 1.8V & 1.2V Power Consumption = (0.3125)(75.8uW) + (0.6875)(213uW) = 170.125 uW  20.13 % Power Reduction

17 December 1, 2005ELEC 6970 - Project Presentation17 32 x 32 bit array Multiplier  N=32   Total Number of Gates = 6N 2 = 6(1024) = 6144  Number of Gates with Low V DD = (N-1)(N+6) = (31)(38) = 1178 = 19.2 % = (31)(38) = 1178 = 19.2 %  Number of Gates with Normal V DD = 6144 – 1178 = 4966 = 80.8% 6144 – 1178 = 4966 = 80.8%

18 December 1, 2005ELEC 6970 - Project Presentation18 Power Estimation  Using Dual-Voltages, 1.8V & 1.5V Power Consumption = (0.192)(8.45mW) + (0.808)(13.63mW) = 12.64 mW  7.3% Power Reduction

19 December 1, 2005ELEC 6970 - Project Presentation19 Power Estimation  Using Dual-Voltages, 1.8V & 1.2V Power Consumption = (0.192)(4.85mW) + (0.808)(13.63mW) = 11.9 mW  12.4% Power Reduction

20 December 1, 2005ELEC 6970 - Project Presentation20 Conclusion Pros…  Reduction in power  Delay is not compromised  No change in Area  Dual-power supply is easy to generate using potential dividers Cons…  The percentage of the circuit that can be fed with Low Voltage supply is less  Requires careful assignment of Low Voltage Supply

21 December 1, 2005ELEC 6970 - Project Presentation21 Comments  Learnt VHDL basics  Introduction to very useful EDA tools  Get a feel of VLSI Design  Appreciation of Low Power Design  Time Consuming but worth it

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