Presentation is loading. Please wait.

Presentation is loading. Please wait.

Silicon VLSI backplanes which shows cracking in the Al mirror Image provided by Dr Neil Collings.

Similar presentations


Presentation on theme: "Silicon VLSI backplanes which shows cracking in the Al mirror Image provided by Dr Neil Collings."— Presentation transcript:

1 Silicon VLSI backplanes which shows cracking in the Al mirror Image provided by Dr Neil Collings

2 Silicon VLSI backplanes showing "punch through" of the transistor underlying the mirror. Image provided by Dr Neil Collings

3 Wafer1.tif: From Mark Mann. First image of CNTs grown by a new type of furnace. This shows morphology and size distribution of the grown nanotubes. SEM was used to compare this across the width of the 4" wafer.

4 Yps42c1.tif: from Mark Mann. Checking for CNTs grown on the top of sharply etched tungsten contained within a Schottky module. The CNT operates as a field emission source. The SEM is used to check the CNT's length & rough diameter. It also checks for alignment.

5 Images provided by: Husnu Emrah Unalan Demonstrating supergrowth Further details awaited

6 Lewis06secondchipTT: Provided by Mark Mann. Fabrication of aligned, sparse arrays of multi-walled carbon nanotubes for use as a field ionizer for mass spectroscopy. Taken at 25 deg. tilt - some tips are >20 um high. They have spacing twice their height for optimum field v current density. The SEM is vital to help achieve a greater uniformity in the grown CNTs.

7 Vertically aligned Multiwalled Carbon Nanotubes Contributed by Shupei Oei We check by SEM for a) alignment b) growth c) morphology- height, width d) identify tip or base- growth, by observing position of catalyst particle. Resolution is not quite sufficient for for imaging of single walled carbon nanotubes.

8 Figure 3.2: SEM images (from CL Choong) of CNT microchannel etched by the Bosch process in deep reactive ion etching (DRIE). MWCNTs grow on horizontal floor but not vertical sidewall of microchannel. (a) Microchannel etched by DRIE scallops structure on vertical side wall generated during DRIE using the Bosch process (b) Microchannel with vertical side wall (c) Close-up view at 20kX magnification (d) Close-up view at 40kX magnification No CNTs on vertical sidewall Forest MWCNTs on horizontal floor 100um20um 1um


Download ppt "Silicon VLSI backplanes which shows cracking in the Al mirror Image provided by Dr Neil Collings."

Similar presentations


Ads by Google