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4/25/2006 ELEC7250: Hill 1 Brad Hill ELEC 7250 Logic Simulator.

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Presentation on theme: "4/25/2006 ELEC7250: Hill 1 Brad Hill ELEC 7250 Logic Simulator."— Presentation transcript:

1 4/25/2006 ELEC7250: Hill 1 Brad Hill ELEC 7250 Logic Simulator

2 4/25/2006ELEC7250: Hill2 Simulation Table  Table created  Gate Name  Fan-in and Fan-out  Input and Output Array  Signal Array  Holds Signal Value during simulation  Set to 0 before each vector is applied

3 4/25/2006ELEC7250: Hill3 Result Tables  Primary Input and Primary Arrays  Contains value of each Input Vectors and Expected Output Vectors  Simulated Circuit Table  Contains Input Vectors and Actual Output Vectors  Simulation Table  Gate Name  Fan-in  Fan-out  These Tables are Used to Determine if there is and error with specific input vectors

4 4/25/2006ELEC7250: Hill4 Diagnosis  Back Track Incorrect Primary Outputs  Trace path to gate that produced Output  Suspected Gates and Signal List are formed  Primary Output is First Suspected Signal  The Gate that it originated from is the First Suspected Gate

5 4/25/2006ELEC7250: Hill5 Diagnosis  Each Signal in the Suspected Signal List is traced to the gate it came from  Gates is added to Suspected Gate List  The Gates Fan-in is used to gather more signals for Suspected Signal List  Removing Primary Inputs if any  Keep Gate and Signal Lists for every incorrect output

6 4/25/2006ELEC7250: Hill6 Diagnosis  It is likely that an Error in one gate will cause many invalid outputs  Each invalid output has its own Suspect list  The different lists can be compared with each other to find which Suspect Gate occurs the most  This Can Aid in Trying to Narrow the Faulty Gate Down

7 4/25/2006ELEC7250: Hill7 Complexity  Depends on Complexity of Circuit  Number of Fan-outs of Gates  Number of Outputs  Number of Gates  Depth of Circuit  Increase in Any of these will result in an increase in execution time

8 4/25/2006ELEC7250: Hill8 Conclusion  Work well with Errors in Gates that are reflected in many Outputs  Work well with Errors in Gates that are reflected in different Outputs given different Inputs  If there are not many Primary Outputs or Fan- outs  Will only provide Possible Paths the Faulty Gate is in  May take considerable execution time with increasing numbers of Gates and Fan-outs

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