1. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 1 ECE 224a Process and Design Rules  Process Overview  Device Fabrication Limits  Derived Layers  Self Alignment/Dual Damascene/CMP  Design Rules  Resolution/Step Coverage/Process  Electrical/Reliability/Mechanical Stress

2. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 2 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

3. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 3 The Manufacturing Process  Photo-Lithography  Mask to Resist  Resist to Pattern Layer  Process (Implant/Etch/Oxide/Nitride/…)  Cleanup (Clean/Planarization/Anneal)  Setup next Layer for Processing For a great reference source: http://www.reed-electronics.com/semiconductor

4. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 4 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

5. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 5 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

6. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 6 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

7. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 7 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p

8. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 8 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

9. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 9 CMOS Process Walk-Through

10. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 10 Advanced Process Modules

11. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 11 80 nm Lines 120 nm Contact Holes Lithography for 0.1um Node

12. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 12 50nm Pre-trim Trim X sec Resist trimming is predictable by computer simulation as well as experiment. Experimental Simulation Trim X+20 sec Poly Gate Etch  100nm

13. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 13 12A Gate Oxide

14. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 14 Advanced Metallization

15. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 15 Cu/Low-k1 Al/Low-k1 22% 15% RC delay is evaluated at minimum M2 pitch Interconnect RC Trend

16. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 16 Design Rules  What can be fabricated?  Resolution Limits –Light Source (357nm, 254nm, 193nm, ?) –Contact/Phase Masking –Surface State (Reflection/Scattering)  Material Limits –Step Coverage –Porosity/Defect Propagation –Mechanical/Thermal Stress

17. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 17 Design Rules II  Electrical Limits –Electrical Fields (MV/cm)! –Parasitic Conductivity/Devices (Latchup/ESD) –Joule Heating (Electro-Migration)  Defect Probability –Contact/Via Replication –Grid-Based Power/Ground Networks  Advance Lithography –Rule Explosion/Failure of Locality –CMP Area Rules/Antenna Rules

18. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 18 845A 85nm Poly Gate Profile

19. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 19 * Fanout = 1 ring oscillator ** room temp. & worst case. CL013 Core Device

20. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 20 * Please refer to shrinkage guideline for non-shrinkable details 0.13/0.18 Comparison

21. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 21 3D Perspective Polysilicon Aluminum

22. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 22 Poly SiGe Poly-SiGe Gate

23. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 23 Design Rules III  Interface twixt designer and process engineer  Unit dimension: Minimum Feature Size  scalable design rules: lambda  absolute dimensions: (Vendor rules)  Process Design Layers  Derived Layers

24. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 24 CMOS Process Design Layers Layer Polysilicon Metal1 Metal2 Metal3 Contact to poly/diff Vias Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Gold Black Select (p+,n+) Green

25. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 25 Intra-Layer Design Rules Metal3 3 5 12 18 0 Well Active 3 3 Polysilicon 3 2 Different Potential Same Potential Metal1/2 3 3 2 Contact or Via Select 2 or 6 2 Hole

26. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 26 Transistor Layout 3.1 FET length 2 (min) 3.2 FET spacing 3 3.3 Poly Overlap 2 3.4 Active Overlap 3 3.5 Space 1

27. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 27 Active Contact I 6.1 Size 2x2 6.2 Enclosure 1.5 6.3 Spacing 3 6.4 Space to FET 2

28. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 28 Poly Contact I 5.1 Size 2x2 5.2 Enclosure 1.5 5.3 Spacing 3 5.4 Space to FET 2

29. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 29 Via (m1 to m2) 8.1 Size 2x2 8.2 Spacing 3 8.3 Enclosure 1 8.4 Space to Contact 2 8.5 Space to Poly/Act 2 9.1 Min Width 3 9.2.a Spacing 3 9.2.b Spacing 6 (width>10) 9.3 Enclosure 1

30. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 30 Select Layer

31. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 31 CMP Density Rules  Chemical-Mechanical Polishing  Requires uniform density of metal/poly  SCMOS Rules:  Poly 30% density across each 1mm 2 area  M1, M2 15% density  M3 (top metal) is not restricted since no further polishing…

32. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 32 Layout Guidelines I  Group Transistors into Cells  Plan inter-cell wires first (Sticks)  Oversize Power Grids (Cell Default >6)  Frequent Substrate Contacts/Well Plugs –Every Well (even one will kill design!) –Max distance to plug/contact 5-8 microns  Set a large user grid e.g. 1-2 lambda  Don’t optimize until you know the constraints  Plan for Change and Optimization

33. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 33 Electromigration (1)

34. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 34 Electromigration (2)

35. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 35 Metal Migration  Al (2.9  cm M.P. 660 C)  1mA/  m 2 at 60C is average current limit for 10 year MTTF  Current density decreases rapidly with temperature  Cu (1.7  cm M.P. 1060 C  10mA/  m 2 at 100C or better (depends on fabrication quality)  Density decreases with temperature, but much slower over practical Silicon operation temperatures <120C  Find Average current through wire – check cross section  Be wary of Via’s!! Typical cross-section: 20-40% of minimal wire.

36. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 36 Layout Guidelines II  Current Limits  1 mA/  m 2 Avg. current limit (50C) –Strongly Temp Dependent (Al) –Failures typically occur at vias and contacts –Vias often Tungsten (higher resistance)  Wide Wires need via arrays!  Transistor Contacts  Active is highly resistive  Avoid High Density Currents

37. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 37 Pads

38. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 38 Pads-- Chip to Board Interface  Pads drive large Capacitances  5pf minimum to much larger  Rise time control  Board Impeadance and Noise  L dI/dt Noise  Coupling to Power Distribution  ESD

39. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 39 Chip Packaging Bond wires (~25  m) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100  m in 0.25  m technology), with large pitch (100  m) Many chips areas are ‘pad limited’ Chip L L Bonding wire Mounting cavity Lead Pin

40. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 40 Pad Frame LayoutDie Photo

41. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 41 Pad Example  Multiple busses provide clean/driver power  VDD/GND pads drive the busses  Output pads have protection circuitry and driver circuitry  Input pads have protection circuitry  Seal Ring  Guard Rings

42. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 42 Bus Detail  Multiple supply rings simplify pad design  Generic Layout Simplifies custom tuning  Guard Rings Between sections of pad  ESD/Driver  Controller

43. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 43 Seal Ring  Seal Ring is essentially a guard ring with metal layers and contacts placed to lower overglass to substrate evenly at chip boundary  Hermetic seal of chip from atmosphere and other contamination

44. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 44 Pad Frame  Large Power Busses Surround Die  ESD in PADS  Driver/Logic in Pads  Seal Ring  Drive Bypass

45. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 45 Chip to Board Interface -- Pad Design  Buffer to drive PCB-scale parasitics  Capacitance 5-50pF, Impedance 30-90   Rise-Time Control  Noise injection to circuits and power supply  ESD  Protection of chip-scale components  Perimeter Pads/Area Bump

46. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 46 Driving Large Capacitances V in V out C L V DD Transistor Sizing Cascaded Buffers

47. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 47 Using Cascaded Buffers C L = 20 pF InOut 12N 0.25  m process Cin = 2.5 fF tp 0 = 30 ps F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns (See Chapter 5)

48. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 48 Output Driver Design Trade off Performance for Area and Energy Given t pmax find N and f  Area  Energy

49. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 49 Delay as a Function of F and N 10 1357 Number of buffer stages N 911 10,000 1000 100 t p / t p 0 F = F = 1000 F = 10,000 t p /t p0

50. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 50 Output Driver Design Transistor Sizes for optimally-sized cascaded buffer t p = 0.76 ns Transistor Sizes of redesigned cascaded buffer t p = 1.8 ns 0.25  m process, C L = 20 pF

51. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 51 How to Design Large Transistors G(ate) S(ource) D(rain) Multiple Contacts small transistors in parallel Reduces diffusion capacitance Reduces gate resistance

52. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 52 Bonding Pad Design Bonding Pad Out In V DD GND 100  m GND Out

53. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 53 ESD Protection  When a chip is connected to a board, there is unknown (potentially large) static voltage difference  Equalizing potentials requires (large) charge flow through the pads  Diodes sink this charge into the substrate – need guard rings to pick it up.

54. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 54 ESD Protection Diode

55. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 55 Packaging

56. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 56 Packaging Requirements  Electrical: Low parasitics  Mechanical: Reliable and robust  Thermal: Efficient heat removal  Economical: Cheap

57. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 57 Bonding Techniques

58. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 58 Tape-Automated Bonding (TAB)

59. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 59 Flip-Chip Bonding

60. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 60 Cu Flip-Chip Technology

61. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 61 Package-to-Board Interconnect

62. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 62 Package Types

63. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 63 Package Parameters

64. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 64 Multi-Chip Modules

65. EE141 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing 65 Lecture Problems 2 1. Why is there a spacing rule between via’s and contacts and/or vias and other vias? How is it eliminated in deeper (smaller) processes? 2. Draw a schematic and stick layout for a 3-input 2-output adder cell (output is sum and carry). Design as two cells: a cell producing ~C out and another cell producing S out (a,b,c,~C out ). Design Sue schematics and Max Layout for the two cells with minimum size transistors and turn in check plots. 3. Guard Rings consist of n and p contact regions with continuous metal connections. They are often used to surround and isolate sensitive devices. How do they work? 4. Very wide metal (any layer) in most technologies needs to have slots cut in it. Why? 5. Explain the relation between CMP planarization and metal/poly density rules. 6. Draw schematics and stick layouts for a 2 of 4 majority gate (true if two or more of its inputs are False). Do two designs, one to minimize transistors, and one where the inputs arrive in order:a,b,c,d last ti minimize the critical path.