1. Presenter: Shao-Jay Hou

2. Embedded logic analysis has emerged as a powerful technique for identifying functional bugs during post- silicon validation, as it enables at-speed acquisition of data from the circuit nodes in real-time. Nonetheless, the amount of data that is observed is limited by the capacity of the on-chip trace buffers. This paper introduces an automated method for improving the utilization of the on- chip storage, by identifying a small set of trace signals from which a large number of states can be restored using a compute-efficient algorithm. This enlarged set of data can then be used to aid the search of functional bugs in the fabricated circuit.

3. To find the bugs(errors) of complex SoC  Scan-Chain  Trace signal The problem of trace in post-silicon validition  Tracer buffer size This limited observability of internal signals may lengthen the debug process, and it motivates our work. Functional bugs Material & manufacture error Unpredictable bugs

4. Trigger Pointer  Start or end of trace Trace Buffer  Where trace signal saved Compression?

5. Signal use Debug use Tracer use My thesis Tracer improve Compression method This paper

6. conference Journal [18]SignalTap [19]ChipScope [18]SignalTap [19]ChipScope [12]postpocessing algorithm [13] propagation trace [12]postpocessing algorithm [13] propagation trace [28]Visibility [10][22]-[24] Silicon debug On-chip buffer base trace ELAs Similar to this paper

7. Forward & Backward

8. restoration ratio: restored+traced/traced

9. To reduce the computing time Use bitwise opearation Define: Karnaugh map

10. Frist, before you read the section, you should know:  topology  BFS(breadth-frist-search)&DFS(depth-frist-search)  greed algorithm 。 Traveling Salesman Problem

11. Define the restorability: Then, use the algorithm to identify the signals:

12. Example for algorithm:

13. Select the signals should be traced by coverage estimation:

14. Restorability define:

16. Environment of experiment  Dual Xeon 2.4GHz  1G Ram

18. The paper proposed 3 useful algorithm for trace data selection  One for state restorability  Two for trace signals selection The contribution I think is for the CPU debug and Cadtool develop, but also a good idea for tracer.

19. Why I choose these two papers?  Detail  Easy to understand  Much examples  Source of this technology The structure of the paper is complete  Clear define  Easy to see the beef of the paper Clear define the parameter in trace signals, maybe the tracer can be use like to the paper.