1. The Multicycle Processor II CPSC 321 Andreas Klappenecker

2. Questions? Problems?

3. Today’s Menu The Multicycle Processor Introduction to Verilog

4. Single memory unit for instructions and data Single arithmetic-logical unit Registers after every major unit (some visible to the programmer, some not) hold output of that unit until value is used in next clock cycle data used in subsequent instructions must be stored in programmer visible registers Multicycle Approach

5. Multicycle Datapath and Control Lines

9. Instruction Fetch/Decode/Execute

10. 3 rd Step: R-Type Instruction

12. 3 rd Step: Memory Reference Instructions Memory Access

14. 4 th Step: Memory Reference Instructions Memory Address Computation Store

16. What Happened So Far? Single-cycle processor Multi-cycle processor Next: Pipelined processor Build your own processor @ home!

17. Verilog

18. Levels of Abstraction Specification Architectural Description Verilog, VHDL, ELLA or other HDLs Logic Design Gates and Registers Circuit Design Transistors sized for power and speed Technology mapping Layout

19. Levels of Abstraction + n+ S G D System Module Gate Circuits Device

20. MOS Transistors PMOS transistor like a switch ON if gate is 1 OFF if gate is 0 NMOS transistor OFF if gate is 1 ON if gate is 0 Drain (+) Drain (-) Source (+) Source (-) Current Flow

21. CMOS Circuits Simple Avoids difficulties Resilient Energy efficient Current flow only during switching time

22. Circuit Design Layering and Fabrication Layout

23. Hardware Description Languages Abstracting from circuits Structural description Specify full adder by NAND and NOR gates Behavioral description Specify full adder by functional behavior Improves productivity Natural for Computer Scientists

24. Verilog Structural description Gates, wires, input/output Hierarchical description possible (define full adder in terms of gates) Behavioral description Abstract formulation Functional relationships

25. Structural Verilog Example module mux(f, a,b,sel); output f; input a,b,sel; wire f1, f2; not(nsel, sel); and(f1, a,nsel); and(f2, b, sel); or (f, f1, f2); endmodule b a sel f

26. Behavioral Verilog Example module mux2(f, a,b,sel); output f; input a,b,sel; assign f = (a & ~sel) | (b & sel); endmodule

27. Another Example module mux2(f, a,b,sel); output f; input a,b,sel; reg f; always @(a or b or sel) if (sel==1) f = b; else f = a; endmodule

28. Synthesis Compilation Verilog code is translated into a network of logic gates Optimization Try to find a better solution by logic optimization (limited success) Technology mapping Physical design

29. Logic Gates and(y, a, b) or(y, a, b) not(y, a) xor(y, a,b) nand(y, a, b) …

30. Modules module mod_name (parameters); input … output … reg … …… endmodule

31. Full Adder module fulladd(cin, x, y, s, cout) input cin, x, y; output s, cout; assign s = x ^ y ^ cin; assign cout = (x & y) | (cin & x) | (cin & y); endmodule

32. Full Adder module fulladd(cin, x,y,s, cout); input cin, x, y; output s, cout; assign { cout, s } = x + y + cin; Endmodule The assign statement sets cout to MSB and s to LSB

33. Verilog Simulators vcs from Synopsis powerful debugging tools Icarus Verilog compiler, free Veriwell simulator, free

34. Information about Verilog Short manual by Chauhan and Blair Verilog Quick Reference Guide by Sutherland HDL Appendix A in Fundamentals of Digital Logic by Brown and Vranesic Quick Reference for Verilog HDL by Rajeev Madhavan

35. Hello World module top; initial $display("Hello, world!"); endmodule initial statements are executed once by the simulator

36. Verilog Simulator The Verilog simulator is event driven Different styles of Verilog structural dataflow behavioral We will see examples of each type

37. Nets A net represents a node in the circuit The wire type connects an output of one element to an input of another element wire abar; not(abar, a); nand(b, abar,abar);

38. Vector wires Range [msb: lsb] wire [3:0] S; S = 4’b0011 The result of this assignment is S[3] = 0, S[2] = 0, S[1] = 1, S[0] = 1 wire [1:2] A; A = S[2:1]; means A[1] = S[2], A[2] = S[1]

39. Variables Variables come in two flavors reg integers reg can model combinatorial or sequential parts of the circuits reg does not necessarily denote a register! Integers often used as loop control variables useful for describing the behavior of a module

40. Simple Example module testgate; reg b, c; // variables wire a, d, e; // nets and (d, b, c); // gates or (e, d, c); // nand(a, e, b); // initial begin // simulated once b=1; c=0; // blocking assignments #10 $display("a = %b", a); end endmodule What value will be printed?

41. Operators 1’s complement ~A 2’s complement -A bitwise AND A&B reduction &A produces AND of all bits in A Concatenate {a,b,c} | {a,b,c} = a | b | c Replication operators 2{A} = {A,A} {2{A},3{B}} = {A,A,B,B,B}

42. Continuous assignments Single bit assignments assign s = x ^ y ^ cin; assign cout = (x & y) | (cin & x) | (cin &y ) Multibit assignments wire [1:3] a,b,c; … assign c = a & b;

43. Full Adder module fulladd(cin, x, y, s, cout) input cin, x, y; output s, cout; assign s = x ^ y ^ cin; assign cout = (x & y) | (cin & x) | (cin & y); endmodule

44. Always Blocks An always block contains one or more procedural statements always @(sensitivity list) always @(x or y) begin s = x ^ y; c = x & y; end

45. Mux: Structural Verilog module mux(f, a,b,sel); input a,b,sel; output f; wire f1, f2; not(nsel, sel); and(f1, a,nsel); and(f2, b, sel); or (f, f1, f2); endmodule b a sel f

46. Conclusion Verilog abstracts hardware Modules represent hardware units You can specify the behavior in structural dataflow-oriented behavioral ways.

47. Mux: Dataflow Model module mux2(f, a,b,sel); output f; input a,b,sel; assign f = (a & ~sel) | (b & sel); endmodule

48. Mux: Behavioral Model module mux2(f, a,b,sel); output f; input a,b,sel; reg f; always @(a or b or sel) if (sel==1) f = b; else f = a; endmodule