1. 1 Design of 4- BIT ALU Swetha Challawar Anupama Bhat Leena Kulkarni Satya Kattamuri Advisor: Dr.David Parent 05/11/2005

2. 2 Agenda Abstract Introduction –Why –Simple Theory Objectives Project (Experimental) Details Results Cost Analysis Conclusions

3. 3 Abstract We designed a 4- bit ALU that operates with a power of 18.96mW/cm2 on an area of 534*459 μm2. It can drive a load up to 30Ff. ALU performs 16 arithmetic and logical functions. Operation frequency is 200Mhz Setup time is 0.63ns and hold time is 0.23ns.

4. 4 Introduction We all know that the ALU is an important component of the CPU. It is the ALU that performs all calculations and comparisons, on the basis of which the computer is able to take further actions. The 4 bit ALU is controlled by four function select inputs(S0 to S3) and the mode Control Input (M). It can perform all the 16 possible logical operations or 16 different arithmetic operations.

5. 5 Objectives To design 4-bit ALU using Cadence Tools To implement the concepts learned in EE166 To learn accurate decision making during design

6. 6 Design Flow Process Implementation of gate level schematic in Cadence to verify the logic using NC Verilog. Finding the Longest Path. Cell based designing followed by checking for 10% specification. Implementation of transistor level schematic in Cadence. Spice Simulation for transistor level Layout DRC Extraction LVS Post Extraction

7. 7 Project Summary Implemented the concepts learnt in EE166 class. Tried to make accurate decisions during the design process. Met all specifications.

8. 8 Gate Level Schematic

9. 9 Functional Table

10. 10 Longest Path Calculations Note: All capacitance values are in fF Wn (H.C)Wp (H.C) cm 3.66E-049.20E-04 6.87E-042.60E-04 2.49E-049.55E-04 3.71E-049.75E-04 3.88E-046.35E-04 3.89E-048.29E-04 3.40E-048.11E-04 2.75E-042.48E-04 2.20E-045.27E-04 2.70E-044.27E-04 5.57E-046.27E-04 2.89E-044.19E-04 3.42E-045.58E-04

11. 11 XOR

12. 12 Top level Schematic

13. 13 Transistor level Schematic

14. 14 Logic Verification for A+B

15. 15 Layout

16. 16 LVS Report

17. 17 Simulations

18. 18 Simulations Power – 18.96mW

19. 19 Cost Analysis –verifying logic: 2 weeks –verifying timing: 1 week –Layout: 2 weeks –post extracted timing: 2 days

20. 20 Conclusion Challenges Encountered –Debugging for LVS and DRC errors –Changed set of XORs to NAND and Inverter What we learnt from this project? –Basic CAD skills –Implementation of metal contacts: when, where and how? –Design flow process –Enhanced decision making skills To select appropriate Wn and Wp Values To define correct cell height in layout.

21. 21 Acknowledgements Thanks to Dr. David Parent for valuable guidance and constant encouragement Thanks to John and EE166 Classmates