1. A Deficit Round Robin Input Arbiter for NetFPGA Jonathan Woodruff

2. Fair Queuing Packetwise Round Robin Isn’t Fair Bitwise Round Robin Is Fair Approximate Downsides: – Adds Complexity – Adds New Queuing Stage Described by John Nagle

3. Deficit Round Robin Counters on the Queues Approximates Fair Queuing Downside: – May Add New Queuing Stage By George Varghese

4. NetFPGA Deficit Round Robin New Queuing Stage Two Flows: –Input Port –Type of Service Input Port Option is Ineffective in Congestion

5. Simple Deficit Round Robin Use the Input Arbiter Queuing Stage Fair Queuing with No Added Complexity Useful When Ports = Flows i.e. at the edge of the network where each port represents a single system.

6. DRR Input Queues

7. Input Arbiter Selector Size Count FIFO 0 Queue 1Queue 2Queue 3Queue 4Queue 5Queue 6Queue 7 Data 6003000

8. Header Parser ?? IP N-Hop IP ARP Route ModuleMAC IP Output Multiplexer 123456789101112 1314151617181920 21 TAIL

9. Input Arbiter Selector 0 Data Data 0 Selector 1 Data 1 Size Count FIFO 0 Queue 1Queue 2Queue 3Queue 4Queue 5Queue 6Queue 7

10. Bandwidth Sharing Mb/s Deficit Quanta

11. Ping vs. Deficit Quanta

12. Throughput vs. Deficit Quanta

13. Questions?