1. Spring 2007EE130 Lecture 34, Slide 1 Lecture #34 OUTLINE The MOS Capacitor: MOS non-idealities (cont.) V T adjustment Reading: Chapter 18.3

2. Spring 2007EE130 Lecture 34, Slide 2 A heavily doped film of polycrystalline silicon (poly-Si) is typically employed as the gate-electrode material in modern MOS devices. –There are practical limits to the electrically active dopant concentration (usually less than 1x10 20 cm -3 )  The gate must be considered as a semiconductor, rather than a metal Poly-Si Gate Depletion P-type Si N+ poly-Si n-type Si P+ poly-Si NMOSPMOS

3. Spring 2007EE130 Lecture 34, Slide 3 How can gate depletion be minimized? MOS Band Diagram with Gate Depletion V G is effectively reduced: EcEc E FS EvEv EvEv qV G qSqS WTWT P-type SiN+ poly-Si gate EcEc qV poly W poly Si biased to inversion:

4. Spring 2007EE130 Lecture 34, Slide 4 N+ poly-Si Gauss’s Law dictates polyox poly qNW/ E  Gate Depletion Effect x o is effectively increased: p-type Si - - - - - - ++++++ N+ ++ - -- C poly C ox

5. Spring 2007EE130 Lecture 34, Slide 5 Example: GDE V ox, the voltage across a 2 nm thin oxide, is 1 V. The n + poly-Si gate active dopant concentration N poly is 8  10 19 cm -3 and the Si substrate doping concentration N A is 10 17 cm -3. Find (a) W poly, (b) V poly, and (c) V T. Solution: (a) nm 3.1 cm108C 6.1cm102 V 1)F/cm(1085.89.3 // 319 7 14        polyoox polyox poly qNxV W  E

6. Spring 2007EE130 Lecture 34, Slide 6 (b) (c) Is the loss of 0.11V significant?

7. Spring 2007EE130 Lecture 34, Slide 7 The average inversion-layer location below the Si/SiO 2 interface is called the inversion-layer thickness, T inv. Inversion-Layer Thickness T inv -50-40-30-20-1001020304050 SiSiO 2 poly-Si gate

8. Spring 2007EE130 Lecture 34, Slide 8 at V G =V dd (V G + V T )/T oxe can be shown to be the average electric field in the inversion layer. T inv of holes is larger than that of electrons because of the difference in effective masses. Effective Oxide Thickness, T oxe

9. Spring 2007EE130 Lecture 34, Slide 9 C Basic LF C-V with gate-depletion with gate-depletion and charge-layer thickness V G data C ox Effective Oxide Capacitance, C oxe

10. Spring 2007EE130 Lecture 34, Slide 10 V T Adjustment by Ion Implantation In modern IC fabrication processes, the threshold voltages of MOS transistors are adjusted by ion implantation: –A relatively small dose N I (units: ions/cm 2 ) of dopant atoms is implanted into the near-surface region of the semiconductor –When the MOS device is biased in depletion or inversion, the implanted dopants add to the dopant-ion charge near the oxide-semiconductor interface.