Presentation is loading. Please wait.

Presentation is loading. Please wait.

ELEN 468 Lecture 81 ELEN 468 Advanced Logic Design Lecture 8 Behavioral Descriptions II.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "ELEN 468 Lecture 81 ELEN 468 Advanced Logic Design Lecture 8 Behavioral Descriptions II."— Presentation transcript:

1 ELEN 468 Lecture 81 ELEN 468 Advanced Logic Design Lecture 8 Behavioral Descriptions II

2 ELEN 468 Lecture 82 Procedural Timing Control Delay control Event control Named events “wait” construct

3 ELEN 468 Lecture 83 Delay Control Operator (#) initial begin #0in1 = 0; in2 = 1; #10 in3 = 1; #40 in4 = 0; in5 = 1; #60 in3 = 0; end initial begin #0in1 = 0; in2 = 1; #10 in3 = 1; #40 in4 = 0; in5 = 1; #60 in3 = 0; end

4 ELEN 468 Lecture 84 Event Control Operator (@) … @ ( eventA or eventB ) begin … @ ( eventC ) begin … end … @ ( eventA or eventB ) begin … @ ( eventC ) begin … end Event -> identifier or expression When “@” is reached Activity flow is suspended The event is monitored Other processes keep going posedge: 0->1, 0->x, x->1 negedge: 1->0, 1->x, x->0 Cannot assign value to the event variable inside the synchronized behavior

5 ELEN 468 Lecture 85 Named Event module modA (…); … event sth_happens; // declaration always … ->sth_happens; // trigger event end endmodule module modB(…); … always @ (top_mod.modA.sth_happens) … endmodule module modA (…); … event sth_happens; // declaration always … ->sth_happens; // trigger event end endmodule module modB(…); … always @ (top_mod.modA.sth_happens) … endmodule Also called abstract event Declared only in module with keyword event Must be declared before it is used Event is triggered by “->” Provide high level inter- module communication without physical details

6 ELEN 468 Lecture 86 Example of Named Event module flop_event ( clk, reset, data, q, q_bar ); inputclk, reset, data; outputq, q_bar; regq; eventup_edge; assign q_bar = ~q; always @ ( posedge clk ) -> up_edge; always @ ( up_edge or negedge reset ) begin if ( reset == 0 ) q = 0; else q = data; end endmodule module flop_event ( clk, reset, data, q, q_bar ); inputclk, reset, data; outputq, q_bar; regq; eventup_edge; assign q_bar = ~q; always @ ( posedge clk ) -> up_edge; always @ ( up_edge or negedge reset ) begin if ( reset == 0 ) q = 0; else q = data; end endmodule

7 ELEN 468 Lecture 87 The “wait” Construct module modA (…); … always begin … wait ( enable ) ra = rb; … end endmodule module modA (…); … always begin … wait ( enable ) ra = rb; … end endmodule Activity flow is suspended if expression is false It resumes when the expression is true Other processes keep going

8 ELEN 468 Lecture 88 Intra-assignment Delay: Blocking Assignment // B = 0 at time 0 // B = 1 at time 4 … #5 A = B; // A = 1 C = D; … A = #5 B; // A = 0 C = D; … A = @(enable) B; C = D; … A = @(named_event) B; C= D; … // B = 0 at time 0 // B = 1 at time 4 … #5 A = B; // A = 1 C = D; … A = #5 B; // A = 0 C = D; … A = @(enable) B; C = D; … A = @(named_event) B; C= D; … If timing control operator(#,@) on LHS Blocking delay RHS evaluated at (#,@) Assignment at (#,@) If timing control operator(#,@) on RHS Intra-assignment delay RHS evaluated immediately Assignment at (#,@)

9 ELEN 468 Lecture 89 Intra-assignment Delay: Non-blocking Assignment always begin @ ( posedge clk ) G <= @ (bus) acc; C <= D; // not blocked end always begin @ ( posedge clk ) G <= @ (bus) acc; C <= D; // not blocked end Sampling RHS immediately in the latest cycle Wait for time control to execute assignment Subsequent assignments are not blocked In 1 st cycle, “acc” is sampled What if no “bus” change in the same cycle? In next cycle, “acc” is sampled again Value of “acc” from previous cycle is overwritten Warning message

10 ELEN 468 Lecture 810 Be Cautious module or8( y, a, b ); input [7:0] a, b; output [7:0] y; reg [7:0] y; initial begin assign y = a | b; end endmodule module or8( y, a, b ); input [7:0] a, b; output [7:0] y; reg [7:0] y; initial begin assign y = a | b; end endmodule Model combinational logic by one-shot (initial) behavior Valid Not preferred Not accepted by synthesis tool

11 ELEN 468 Lecture 811 Example initial begin a = #10 1; b = #2 0; c = #3 1; end initial begin d <= #10 1; e <= #2 0; f <= #3 1; end initial begin a = #10 1; b = #2 0; c = #3 1; end initial begin d <= #10 1; e <= #2 0; f <= #3 1; end t a b c d e f 0 x x x x x x 2 x x x x 0 x 3 x x x x 0 1 10 1 x x 1 0 1 12 1 0 x 1 0 1 15 1 0 1 1 0 1

12 ELEN 468 Lecture 812 Tell the Differences always @ (a or b) y = a|b; always @ (a or b) #5 y = a|b; always @ (a or b) y = #5 a|b; always @ (a or b) y <= #5 a|b; always @ (a or b) y = a|b; always @ (a or b) #5 y = a|b; always @ (a or b) y = #5 a|b; always @ (a or b) y <= #5 a|b; Event control is blocked Which one describes or gate?

13 ELEN 468 Lecture 813 Simulation of Assignments For each given time step Evaluate all Right-Hand-Side Execute blocking assignment Execute non-blocking assignment that do not have intra-assignment timing control Execute past non-blocking assignment that is scheduled at this time Execute $monitor. However, $display is executed whenever it is encountered. Increment time step

14 ELEN 468 Lecture 814 Simulation of Non-blocking Assignment Normally the last assignment at certain simulation time step If it triggers other blocking assignments, it is executed before the blocking assignment it triggers always … begin A <= B; end … always … begin C = @(A) D; end always … begin A <= B; end … always … begin C = @(A) D; end

15 ELEN 468 Lecture 815 Example initial begin a = 1; b = 0; a <= b; b <= a; $display(“a=%b b=%b”, a, b); end initial begin a = 1; b = 0; a <= b; b <= a; $display(“a=%b b=%b”, a, b); end initial begin a = 1; b = 0; a <= b; b <= a; $monitor(“a=%b b=%b”, a, b); end initial begin a = 1; b = 0; a <= b; b <= a; $monitor(“a=%b b=%b”, a, b); end a=1 b=0 a=0 b=1

16 ELEN 468 Lecture 816 Repeated Intra-assignment Delay regA = repeat (5) @ ( negedge clk ) regB; begin tmp = regB; @ ( negedge clk ); regA = tmp; end begin tmp = regB; @ ( negedge clk ); regA = tmp; end

17 ELEN 468 Lecture 817 Indeterminate Assignment module multi_assign(); reg a, b, c, d; initial begin #5 a = 1; b = 0; end always @ ( posedge a ) begin c = a; end always @ ( posedge a ) begin c = b; end always @ ( posedge a ) begin d = b; end always @ ( posedge a ) begin d = a; end endmodule module multi_assign(); reg a, b, c, d; initial begin #5 a = 1; b = 0; end always @ ( posedge a ) begin c = a; end always @ ( posedge a ) begin c = b; end always @ ( posedge a ) begin d = b; end always @ ( posedge a ) begin d = a; end endmodule Multiple assignments are made to same variable in different behavior Value depends on code order or vendor specifications Similar to race- conditions in hardware

Download ppt "ELEN 468 Lecture 81 ELEN 468 Advanced Logic Design Lecture 8 Behavioral Descriptions II."

Similar presentations

Digital System Design-II (CSEB312)

Digital System Design-II (CSEB312)
Recap : Always block module and_gate (out, in1, in2); inputin1, in2; outputout; regout; or in2) begin out = in1 & in2; end endmodule zAlways.

Recap : Always block module and_gate (out, in1, in2); inputin1, in2; outputout; regout; or in2) begin out = in1 & in2; end endmodule zAlways.
CS 3850 Lecture 6 Tasks and Functions. 6.1 Tasks and Functions Tasks are like procedures in other programming languages. e. g., tasks may have zero or.

CS 3850 Lecture 6 Tasks and Functions. 6.1 Tasks and Functions Tasks are like procedures in other programming languages. e. g., tasks may have zero or.
Simulation executable (simv)

Simulation executable (simv)
Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.

Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.
Synchronous Sequential Logic

Synchronous Sequential Logic
Combinational Logic.

Combinational Logic.
ELEN 468 Lecture 21 ELEN 468 Advanced Logic Design Lecture 2 Hardware Modeling.

ELEN 468 Lecture 21 ELEN 468 Advanced Logic Design Lecture 2 Hardware Modeling.
Hardware Description Language (HDL)

Hardware Description Language (HDL)
Verilog. 2 Behavioral Description initial:  is executed once at the beginning. always:  is repeated until the end of simulation.

Verilog. 2 Behavioral Description initial:  is executed once at the beginning. always:  is repeated until the end of simulation.
2/9/20031 ECE 551: Digital System Design & Synthesis Lecture Set 4 4.1: Verilog – Procedural Assignments &Scheduling Semantics 4.2: Verilog – More Behavioral.

2/9/20031 ECE 551: Digital System Design & Synthesis Lecture Set 4 4.1: Verilog – Procedural Assignments &Scheduling Semantics 4.2: Verilog – More Behavioral.
 HDLs – Verilog and Very High Speed Integrated Circuit (VHSIC) HDL  „ Widely used in logic design  „ Describe hardware  „ Document logic functions.

 HDLs – Verilog and Very High Speed Integrated Circuit (VHSIC) HDL  „ Widely used in logic design  „ Describe hardware  „ Document logic functions.
Specifies combinational logic (unclocked) always stmt. should use “=“ (called “blocking” assignment) in comb. logic always statements. RHS just takes output.

Specifies combinational logic (unclocked) always stmt. should use “=“ (called “blocking” assignment) in comb. logic always statements. RHS just takes output.
ECE 551 Digital System Design & Synthesis Lecture 09 Synthesis of Common Verilog Constructs.

ECE 551 Digital System Design & Synthesis Lecture 09 Synthesis of Common Verilog Constructs.
ELEN 468 Lecture 151 ELEN 468 Advanced Logic Design Lecture 15 Synthesis of Language Construct I.

ELEN 468 Lecture 151 ELEN 468 Advanced Logic Design Lecture 15 Synthesis of Language Construct I.
OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.

OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.
ELEN 468 Lecture 91 ELEN 468 Advanced Logic Design Lecture 9 Behavioral Descriptions III.

ELEN 468 Lecture 91 ELEN 468 Advanced Logic Design Lecture 9 Behavioral Descriptions III.
Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.

Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.
ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II.

ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II.
Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.

Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.

Similar presentations

Ads by Google