1. 1 COMP541 Combinational Logic and Design Montek Singh Jan 25, 2007

2. 2Topics  What we didn’t cover last time Other gates, standard forms Other gates, standard forms  Combinational Design (Ch. 3)  Real Devices Logic Families, Actual ICs, Gate delays Logic Families, Actual ICs, Gate delays  Propagation delay

3. 3 Combinational Logic Design  Ch. 3 takes us to hierarchical design  Like you’d use for a program of size

4. 4 Design Hierarchy  Just like with large program, to design a large chip need hierarchy  Divide and Conquer To create, test, and also to understand To create, test, and also to understand  Block is equivalent to object

5. 5Example  9-input odd func (parity for byte)  Block for schematic is box with labels

6. 6 Design Broken Into Modules Use 3-input odd functions

7. 7 Each Module uses XOR

8. 8 Use NAND to Implement XOR  In case there’s no XOR, for example

9. 9 Design Hierarchy

10. 10 Components in Design  RHS shows what must be designed

11. 11 Reuse is Common  Certainly forced because of availability of parts (chips)  Also the design cycle was very long  Now more flexibility with programmable logic But still reuse from libraries or intellectual property (IP) But still reuse from libraries or intellectual property (IP) Example: buy a PCI design Example: buy a PCI design Open source, see www.opencores.org Open source, see www.opencores.orgwww.opencores.org  Note the many logic blocks available in Xilinx library

12. 12 Flow of CAD System Netlist is description of connections Generic Gates Replaces Generic Gates with ones available in Technology Library

13. 13 Technology Mapping  Full custom Pixel-Planes chips (machines in lobby) Pixel-Planes chips (machines in lobby) Memories, CPUs, etc Memories, CPUs, etc  Standard cell Library of cells Library of cells Engineer determined interconnection Engineer determined interconnection  Gate arrays Small circuits with interconnect Small circuits with interconnect

14. 14 Hierarchy Example – 4-bit Equality  Example 3-4 in book  Input: 2 vectors A(3:0) and B(3:0)  Output: One bit, E, which is 1 if A and B are bitwise equal, 0 otherwise

15. 15Design  Hierarchical design seems a good approach  One module/bit  Final module for E

16. 16 Design for MX module  Logic function in book is  I’d call this “not E”, but…  Can implement as

17. 17 Design for ME module  Final E is 1 only if all intermediate values are 0  So  And a design is

18. 18 Hierarchical Verilog  We already saw example of instantiation when we used AND and OR gates  Just use module name and an identifier for the particular instance

19. 19 Vector of Wires (Bus)  Denotes a set of wires input [1:0] S;  Syntax is [a: b] where a is high-order So this could be “[0:1] S” So this could be “[0:1] S” Order will matter when we make assignments with values bigger than one bit Order will matter when we make assignments with values bigger than one bit Or when we connect sets of wires Or when we connect sets of wires  NOTE: THIS IS NOT AN ARRAY!

20. 20DEMO  Let’s try entering the hierarchical example

21. 21 Next slides document design  Just for your notes

22. 22MX module mx(A, B, E); input A, B; output E; assign E = (~A & B) | (A & ~B); endmodule

23. 23ME module me(E, Ei); input [3:0] Ei; output E; assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]); endmodule

24. 24 Top Level module top(A, B, E); input [3:0] A; input [3:0] B; output E; wire [3:0] Ei; mx m0(A[0], B[0], Ei[0]); mx m1(A[1], B[1], Ei[1]); mx m2(A[2], B[2], Ei[2]); mx m3(A[3], B[3], Ei[3]); me me0(E, Ei); endmodule

25. 25 Integrated Circuit  Known as IC or chip  Silicon containing circuit Later in semester we’ll examine design and construction Later in semester we’ll examine design and construction Maybe processes Maybe processes  Packaged in ceramic or plastic From 4-6 pins to hundreds From 4-6 pins to hundreds  Pins wired to pads on chip

26. 26Bonding

27. 27 Levels of Integration  SSI Individual gates Individual gates  MSI Things like counters, single-block adders, etc. Things like counters, single-block adders, etc. Like stuff we’ll be doing next Like stuff we’ll be doing next  LSI  VLSI Larger circuits, like the FPGA, Pentium, etc. Larger circuits, like the FPGA, Pentium, etc.

28. 28 Logic Families  RTL, DTL earliest  TTL was used 70s, 80s Still available and used occasionally Still available and used occasionally 7400 series logic, refined over generations 7400 series logic, refined over generations  CMOS Was low speed, low noise Was low speed, low noise Now fast and is most common Now fast and is most common  BiCMOS and GaAs Speed Speed

29. 29Catalogs  Catalog pages describe chips  Look at http://focus.ti.com/lit/ds/scas014c/scas014c.pdf  Specifications Pinouts Pinouts Packages/Dimensions Packages/Dimensions Electrical characteristics Electrical characteristics

30. 30 Electrical Characteristics  Fan in – max number of inputs to a gate  Fan out – how many standard loads it can drive (load usually 1)  Voltage – often 1.8v, 3.3v or 5v are common  Noise margin – how much electrical noise it can tolerate  Power dissipation – how much power chip needs TTL high TTL high Some CMOS low (but look at heat sink on a Pentium) Some CMOS low (but look at heat sink on a Pentium)  Propagation delay – next

31. 31 Propagation Delay  Max of high-to-low and low-to-high  Maximum and typical given

32. 32Delays  Transport delay = “pure” delay Output after a specified time Output after a specified time  Inertial delay No effect if input occurs for time that is too short (can’t overcome inertia) – smaller than transport delay time No effect if input occurs for time that is too short (can’t overcome inertia) – smaller than transport delay time

33. 33 Effect of Transport Delay (blue)  Delay just shifts signal in time

34. 34 Effect of Inertial Delay Blue – Propagation delay time Black – Rejection time

35. 35 Fan Out and Delay  Practical fan out of CMOS limited by capacitance of input gates  More gates driven, longer time for signal to change  So delay time for CMOS affected by fan out  Wire delay also very important And routing delays in FPGA And routing delays in FPGA

36. 36 Example using ISE  Look at Lab 1 (tomorrow) Synthesis report timing prediction Synthesis report timing prediction Text-based Post Place & Route timing report Text-based Post Place & Route timing report View routed design View routed design  To see where components and I/O buffers are located

37. 37Today  Design paradigm Hierarchical design Hierarchical design  Talked about real devices  Propagation delays First look at how fast your circuits could work First look at how fast your circuits could work

38. 38 Next Time  Basic combinational circuits Multiplexer Multiplexer Encoders Encoders Decoders Decoders

39. 39Read  Chapter 4 Sections 3, 4, 5 Sections 3, 4, 5 Section 4-8 covers Verilog Section 4-8 covers Verilog