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Introduction to Computer Engineering by Richard E. Haskell Xilinx CPLDs Lab 2b Module M2.4.

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Presentation on theme: "Introduction to Computer Engineering by Richard E. Haskell Xilinx CPLDs Lab 2b Module M2.4."— Presentation transcript:

1 Introduction to Computer Engineering by Richard E. Haskell Xilinx CPLDs Lab 2b Module M2.4

2 Introduction to Computer Engineering by Richard E. Haskell PLDT-1 Trainer Xilinx XC95108 CPLD

3 Introduction to Computer Engineering by Richard E. Haskell XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE 1149.1 JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

4 Introduction to Computer Engineering by Richard E. Haskell XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

5 Introduction to Computer Engineering by Richard E. Haskell XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O 3672108144216 8001600240032004800 57.5 10 3672108144216 3472108133166 Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 288 6400 10 288 192 HQ208 BG352 PQ160 HQ208 BG352 957295108951449521695288

6 Introduction to Computer Engineering by Richard E. Haskell Xilinx Project Navigator

7 Introduction to Computer Engineering by Richard E. Haskell

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