1. 11/19/2004EE 42 fall 2004 lecture 341 Lecture #34: data transfer Last lecture: –Example circuits –shift registers –Adders –Counters This lecture –Communications synchronous / asynchronous –Buses –Start transmission lines

2. 11/19/2004EE 42 fall 2004 lecture 342 Data transfer In addition to computation, it is necessary to transmit information from one place to another. Buses are used to move data from one logic device to another in parallel If the devices are close together, the delay is the RC time to charge the capacitance. If the devices are further apart, need to consider propagation velocity, distortion, crosstalk.

3. 11/19/2004EE 42 fall 2004 lecture 343 Multiplexer vs tri-state/bus To send information to several different destinations, you can just run wires to each of the destinations. But to have information from several sources go to the same destination, you need to control which device drives the destination, can not tolerate pulling up and down on the same wire. This can be done using multiplexers, or by using tri-state drivers in a bus architecture

4. 11/19/2004EE 42 fall 2004 lecture 344 Multiplexer For example, if you have four inputs, you would need a 2 selector 4 input multiplexer for each bit of output. I1I2I3I4I1I2I3I4 2 input decoder ABAB O

5. 11/19/2004EE 42 fall 2004 lecture 345 Bus with tri-state drivers To efficiently route information from many source, a bus can be driven by tri-state drivers. The logic must ensure that only one driver is active at a time.

6. 11/19/2004EE 42 fall 2004 lecture 346 Bus A bus may be synchronous, to a clock edge for example, or asynchronous with handshaking and control lines Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Clock

7. 11/19/2004EE 42 fall 2004 lecture 347 Synchronous v. Asynchronous Clock Signal Handshake Control Asynchronous Circuit Synchronous Circuit

8. 11/19/2004EE 42 fall 2004 lecture 348 Synchronous In a synchronous circuit, there is an explicit global synchronization through the clock signal. The clock period is chosen to be longer than the worst case delay (gate delays + transmission delays)

9. 11/19/2004EE 42 fall 2004 lecture 349 Asynchronous circuit RRRR Req Ack Synchronization with Req / Ack handshakes Logic

10. 11/19/2004EE 42 fall 2004 lecture 3410 asynchronous Asynchronous design is often unavoidable: –User interfaces –Different speed devices –Clocks are difficult to distribute over long distances More difficult to design, design tools generally have been synchronous only, but asynchronous design tools are being developed. Most current devices us synchronous logic inside local blocks, and asynchronous communication between blocks. What constitutes a “block” is shrinking as logic speeds increase. –Currently making jump to chips with multiple independent blocks, or fully asynchronous logic.

11. 11/19/2004EE 42 fall 2004 lecture 3411 Metastability and Asynchronous inputs Clocked synchronous circuits –Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock) –E.g., master/slave, edge-triggered Asynchronous circuits –Inputs, state, and outputs sampled or changed independently of a common reference signal (glitches/hazards a major concern) –E.g., R-S latch Asynchronous inputs to synchronous circuits –Inputs can change at any time, will not meet setup/hold times –Dangerous, synchronous inputs are greatly preferred –Cannot be avoided (e.g., reset signal, memory wait, user input)

12. 11/19/2004EE 42 fall 2004 lecture 3412 Synchronous communication Clock edges determine the time instants where data must be sampled Data wires may glitch between clock edges (data must be stable for set–up/hold times) 110010

13. 11/19/2004EE 42 fall 2004 lecture 3413 In is asynchronous and fans out to D0 and D1 one FF catches the signal, one does not State of Q 0 and Q 1 is inconsistent In Q 0 Q 1 CLK Handling Asynchronous Inputs (cont’d) What can go wrong? –Input changes too close to clock edge (violating setup time constraint)

14. 11/19/2004EE 42 fall 2004 lecture 3414 small, but non-zero probability that the FF output will get stuck in an in-between state oscilloscope traces demonstrating synchronizer failure and eventual decay to steady state logic 0 logic 1 logic 0 logic 1 Synchronization Failure Occurs when FF input changes close to clock edge –FF may enter a metastable state – neither a logic 0 nor 1 – –May stay in this state an indefinite amount of time –Is not likely in practice but has some probability

15. 11/19/2004EE 42 fall 2004 lecture 3415 D D Q Q asynchronous input synchronized input synchronous system Clk Dealing with Synchronization Failure Probability of failure can never be reduced to 0, but it can be reduced –(1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems –(2) use fastest possible logic technology in the synchronizer: this makes for a very sharp "peak" upon which to balance –(3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)

16. 11/19/2004EE 42 fall 2004 lecture 3416 Q D Clk=1 R S Q’ negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input characteristic equation Q(t+1) = D holds D' when clock goes low holds D when clock goes low Edge-Triggered Flip-Flops More efficient solution: only 6 gates –sensitive to inputs only near edge of clock signal (not while high)

17. 11/19/2004EE 42 fall 2004 lecture 3417 clock data changingstable input clock T su ThTh clock data DQDQ Definition: Set up time/hold time To ensure that the data signal is captured accurately, the data must be stable for an time t su (set up) before the edge, and kept constant for a time t h (hold) after the edge.

18. 11/19/2004EE 42 fall 2004 lecture 3418 DQDQ Q0 Clock Q1 Async Input DQ DQ Q0 Clock Q1 Async Input DQ Clocked Synchronous System Synchronizer Handling Asynchronous Inputs If you have to deal with an input which could change at any time, not under you control, what do you do? Never allow asynchronous inputs to fan-out to more than one flip- flop –Synchronize as soon as possible and then treat as synchronous signal

19. 11/19/2004EE 42 fall 2004 lecture 3419 Asynchronous Logic RRRR Req Ack Current practice is starting to embrace asynchronous logic design even on a single chip Logic

20. 11/19/2004EE 42 fall 2004 lecture 3420 Key Design Differences Synchronous logic design: –Does not need to take timing correctness (hazards) into account in many cases –Combinational logic and memory latches are built separately –Static timing analysis of the logic is sufficient to determine the max delay and the required clock period.

21. 11/19/2004EE 42 fall 2004 lecture 3421 Difficulties with asynchronous design Synchronous logic: –Only functional correctness aspect must be verified and tested Asynchronous logic: –In addition to functional correctness, timing must be analyzed –Operation may change for each different operation and operation rate –Testing is more difficult –Most circuit designers learn only synchronous design. –Most CAD tools only support synchronous design. –Asynchronous circuit CAD tools are being developed.

22. 11/19/2004EE 42 fall 2004 lecture 3422 Clock skew A major difficulty with synchronous communications is the fact that the clock must also travel some distance. The clock being different from one place in a circuit to another is called clock skew. For communications over a distance of a meter or so, parallel busses are being abandoned in favor of higher speed asynchronous serial communications. Examples parallel  USB PCI  PCI express

23. 11/19/2004EE 42 fall 2004 lecture 3423 parallel inputs parallel outputs serial transmission Serial transmission Parallel-to-serial conversion for serial transmission

24. 11/19/2004EE 42 fall 2004 lecture 3424 Long signal paths Signal delay –Component delay + interconnection delay Signal integrity Reflections Waveform distortion Signal attenuation Crosstalk

25. 11/19/2004EE 42 fall 2004 lecture 3425 Gate delay So far, the only delay that we have considered is the time needed to charge up the capacitance due to lines, and due to the capacitance of the gates of the next stage. This implies that if we could only push enough current, we can make the delay as short as we like. Wire Gates R

26. 11/19/2004EE 42 fall 2004 lecture 3426 Gate delay If we want to speed up logic, we can increase the drive –reduce the pull up and pull down resistance or we can reduce the capacitance. –Shorter lines, narrower lines, reduced dielectric constant of dielectric between wires. This is limited, however by the speed of light

27. 11/19/2004EE 42 fall 2004 lecture 3427 Light speed With lines that are long enough, or switching speeds are high enough, then we can not consider the delay to be simply that due to charging up the capacitance. The signal will propagate along a wire at the speed of light (in the dielectric, which is slower than that in air or vacuum) Quite a bit of current is necessary to pull up a line that fast, for a 1 volt signal, 10-20 milliamps are required.

28. 11/19/2004EE 42 fall 2004 lecture 3428 Transmission Line When a signal wire is driven with that fast a rise time compared to its length, a signal will travel along the wire at the speed of light in the media. It is even possible to turn off the current, and have the pulse that is already on the line continue to propagate toward the destination So you don’t have to wait for one bit to arrive before you send the next

29. 11/19/2004EE 42 fall 2004 lecture 3429 Transmission Line As the voltage pulses propagate down the line, there is a current pulse which travels down the line with them. The current is always balanced between two conductors, for example forward in one conductor, and backward in the other

30. 11/19/2004EE 42 fall 2004 lecture 3430 Transmission Line Voltage Current in (+) signal line Current in (-) signal line, or current in ground If the signal is conducted in a pair of lines, it is called a balanced line. If the return path is through a ground, it is called unbalanced

31. 11/19/2004EE 42 fall 2004 lecture 3431 Transmission line impedance The ratio of the voltage of propagating pulses to the current the carry is a constant, called the impedance of the line A typical transmission line impedance is 50-100 ohms. When a line is being used in this fashion, it can not be split into two, because for a given voltage, twice as much current would be needed So digital transmission lines do not branch, there is only one path from one end to another.

32. 11/19/2004EE 42 fall 2004 lecture 3432 Transmission line termination Since a transmission line carries pulses of voltage and current, there must be somewhere for the current to go. FET devices are very high impedance, so they don’t absorb that current All that is required to absorb the current at the end of the transmission line is a resistor which has the same resistance as the impedance of the line R termination =Z 0