1. Lab3-1 張明峰 交大資工系 Lab 4: FPGA Implementation Specification RTL design and Simulation Logic Synthesis Gate Level Simulation ASIC LayoutFPGA Implementation

2. Lab3-2 張明峰 交大資工系 Why Top-Down? Design of complex systems Reduce time-to-market –shorten the design verification loop –focus on functionality Easier and cheaper to explore different design option

3. Lab3-3 張明峰 交大資工系 RTL Design Characteristics –fully clock driven RTL code with some behavioral constructs –contain complete functional description –cycle accurate Coding style –structural description (component connections/net-list) –data flow description (continuous assignment) –RTL description (always block) combinational RTL sequential RTL

4. Lab3-4 張明峰 交大資工系 Logic Synthesis Translate synthesizable RTL code to gate-level design Always @(posedge clk) begin if(sel1) begin if(sel2) out = in1 ; else out = in2 ; else if(sel3) if(sel4) out = in3 ; else out = in4 ; end endmodule Gate-level circuits

5. Lab3-5 張明峰 交大資工系 Structural Mapping

6. Lab3-6 張明峰 交大資工系 Resource Sharing Example if (op_code ==0) r = a + c ; else r = a + b ; Sharing –a single ALU for the two additions –a MUX for the second input of the ALU No-Sharing –two adders for the two additions –an output MUX to select the output

7. Lab3-7 張明峰 交大資工系 Register Inferencing Determines which signals must be preserved across cycle boundaries –incomplete logic specification (missing branches) –explicit register instantiation always @(posedge clk) –signal used before assigned

8. Lab3-8 張明峰 交大資工系 Two-level Logic Optimization AND-OR representations –easy implementation as PLAs and PLDs –a key optimization technique –efficient algorithms and heuristics exist –in commercial use for several years –minimize the number of product terms Example –F = XYZ + XY’Z’ + XY’Z + X’YZ + XYZ –F = XY’ + YZ

9. Lab3-9 張明峰 交大資工系 Multi-Level Logic Optimization Meet performance or area constraints through restructuring and simplifications –two-level minimization –common factor extraction –common expression resubstitution Trade-off between area and delay In commercial use for several years –f 1 = abcd+abce+ab’cd’+ab’c’d+a’c+cdf+abc’d’e’+ab’c’df’ –f 2 = bdg + b’dfg + b’d’g+bd’eg –f 1 = c(a’+x)+ac’x’ –f 2 = gx –x = d(b+f) + d’(b’+e)

10. Lab3-10 張明峰 交大資工系 Technology Mapping Translation of a technology independent representation of a circuit into a circuit in a given technology with optimal cost Optimization criteria –minimum area –minimum delay –meeting specified timing constraints –meeting specified timing constraints with minimum area Usages –Technology mapping after technology independent logic optimization

11. Lab3-11 張明峰 交大資工系 Sample covers

12. Lab3-12 張明峰 交大資工系 State Machine Synthesis Translate state table or graph –state minimization –state assignment to minimize the cost function Challenges –state machine decomposition –state assignment for performance –state assignment for testability –extract state graph from implementation

13. Lab3-13 張明峰 交大資工系 Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible I/O interfaces –From 86 to 284 I/Os –16 signal standards  Advanced 0.25/0.22um 6-Layer Metal Process  High performance –System frequency as high as 200 MHz  Advanced Clock Control with 4 Dedicated DLLs  Unlimited Re-programmability  Fully PCI Compliant

14. Lab3-14 張明峰 交大資工系 Spartan-II Top-level Architecture Configurable logic blocks –Implement logic here! I/O blocks –Communicate with other chips –Choose from 16 signal standards Block RAM –On-chip memory for higher performance

15. Lab3-15 張明峰 交大資工系 Spartan-II Top-level Architecture Clocks and delay locked loops –Synchronize to clock on and off chip Rich interconnect resources –Three-state internal buses Power down mode –Lower quiescent power

16. Lab3-16 張明峰 交大資工系 CLB Slice (Simplified) 1 CLB holds 2 slices Each slice contains two sets of the following: –Four-input LUT Any 4-input logic function Or 16-bit x 1 RAM Or 16-bit shift register

17. Lab3-17 張明峰 交大資工系 CLB Slice (cont’d) Each slice contains two sets of the following: –Carry & control Fast arithmetic logic Multiplier logic Multiplexer logic –Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control

18. Lab3-18 張明峰 交大資工系 CLB MUXF6 Slice LUT MUXF5 Slice LUT MUXF5 Dedicated Expansion Multiplexers MUXF5 combines 2 LUTs to form –4x1 multiplexer –Or any 5-input function MUXF6 combines 2 slices to form –8x1 multiplexer –Or any 6-input function

19. Lab3-19 張明峰 交大資工系 I/O Block (Simplified) Registered input, output, 3-state control Programmable slew rate, pull-up, pull-down, keeper and input delay

20. Lab3-20 張明峰 交大資工系 I/O Interface Standards I/O can be programmed for 16 different signal standards –VCCO controls maximum output swing –VREF sets input, output, three-state control Different banks can support different standards at the same time –Logic level translation –Boards with mixed standards

21. Lab3-21 張明峰 交大資工系 IOBs Organized As Independent Banks As many as eight banks on a device –Package dependent Each bank can be assigned any of the 16 signal standards

22. Lab3-22 張明峰 交大資工系 2ns CLB Array High Performance Routing Hierarchical routing –Singles, hexes, longs Sparse connections on longer interconnects for high speed Routing delay depends primarily on distance –Direction independent –Device-size independent Predictable for early design analysis

23. Lab3-23 張明峰 交大資工系 Power-down Mode Controlled by single power down pin All inputs blocked, appear low internally All outputs disabled All register states preserved Power-down status pin Synchronous wake up 100 uA typical

24. Lab3-24 張明峰 交大資工系 There are four ways to program a Spartan-II FPGA Configuration Modes

25. Lab3-25 張明峰 交大資工系 Spartan-II Family Overview

26. Lab3-26 張明峰 交大資工系 Spartan-II Architecture Summary  Delivers all the key requirements for ASIC replacement –200,000 gates –200 MHz –Flexible I/O interfaces –On-chip distributed and block RAM –Clock management –Low power –Complete development system support

27. Lab3-27 張明峰 交大資工系 Design Tools Standard CAE entry and verification tools Xilinx Implementation software implements the design –The design is optimized for best performance and minimal size –Graphical User Interface and Command Line Interface –Easy access to other Xilinx programs –Manages and tracks design revisions Functional Simulation Back Annotation Schematic, State Mach., HDL Code, LogiBLOX, CORE Gen Design Implementation Verification Static Timing Analysis, In-Circuit Testing Design Entry Simulator M1 Design Manager Xilinx Foundation or Alliance

28. Lab3-28 張明峰 交大資工系 Foundation Project Manager Integrates all tools into one environment

29. Lab3-29 張明峰 交大資工系 Schematic Entry

30. Lab3-30 張明峰 交大資工系 ABEL, Verilog and VHDL Text Entry From schematic menu (or via HDL Editor), select Hierarchy -> New Symbol Wizard… to create symbol. Select HDL Editor & Language Assistant to learn by example, then define block. Synthesize to EDIF. 54312

31. Lab3-31 張明峰 交大資工系 State Machine Graphical Editor  Graphical editor synthesizes into ABEL or VHDL code

32. Lab3-32 張明峰 交大資工系 Simulation - Easy to Use and Learn Generate stimulus easily and quickly –Keyboard toggling –Simple clock stimulus –Custom formulas Easy debugging –Waveform viewer –Signals easily added and removed –Simulator access from schematic –Color-coded values on schematic Script Editor

33. Lab3-33 張明峰 交大資工系 What is Implementation? More than just “Place & Route” Implementation includes many phases –Translate: Merge multiple design files into a single netlist –Map: Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) –Place & Route: Place components onto the chip, connect them, and extract timing data into reports –Timing (Sim): Generate a back-annotated netlist for timing simulation tools –Configure: Generate a bitstream for device configuration

34. Lab3-34 張明峰 交大資工系 Terminology Project –Source file; has a defined working directory and family Version –A Xilinx netlist translation of the schematic –Multiple Versions result from iterative schematic changes Revision –An implementation of a Xilinx netlist –Multiple revisions typically result from different options Part type –Specified at translation; can be changed in a new revision

35. Lab3-35 張明峰 交大資工系 Starting the Flow Engine Foundation Project Manager

36. Lab3-36 張明峰 交大資工系 The Flow Engine Implementation phases Implementation status Message area Flow control buttons

37. Lab3-37 張明峰 交大資工系 XSA-50 Board –Xilinx XC2S50 –7-seg LED –100 MHz prog. osc. –SDRAM 8M*8 –Flash 128K bytes –XC9572XL –Parallel port –PS/2 port –VGA port

38. Lab3-38 張明峰 交大資工系 Xstend Board –2 7-seg LED –Bargraph LED –Dip switch –Pushbuttons –Stereo Audio I/O –RS-232 –USB 1.1

39. Lab3-39 張明峰 交大資工系 Lab 4: 7-Segment Decoder input [3:0] sig ; // 0-F output [6:0] control ; // active high

40. Lab3-40 張明峰 交大資工系 4-bit Magnitude Comparator input [3:0] a, b ; input agb, alb, aeb ; 11 input pins XSTend Board S1 XSA-50 board SW1 S1Pin Number 1 30 2 58 3 74 4 75 5 66 6 77 7 80 8 79 SW1Pin Number 154 264 363 456

41. Lab3-41 張明峰 交大資工系 4-bit Magnitude Comparator output agbo, albo, aebo ; Use XSTend Board –Bar LEDs Pin Number D168 D244 D346 D449 D557 D662 D760 D867 D939 D1059