1. R Frey 9/15/20031 Si/W ECal Update Outline Progress on silicon and tungsten Progress on readout electronics EGS4 v Geant4 Ray Frey M. Breidenbach, D. Freytag, G. Haller, O. Milgrome, N. Graf Stanford Linear Accelerator Center RF, D. Strom U. Oregon

2. R Frey 9/15/20032 Component Status: W, Si, readout W plates to make first full prototype arrive UO this week  24 (20) plates, 25 mm x 6”x6”, 92.5% W, non-mag.  12 (10) plates, 50 mm x 6”x6”, same alloy  Cu heat layer likely not needed – use the W to conduct More study in progress Silicon  Order for 10 prototype detectors sent to vendor today !  Have readied test bench(es) to receive them (3 months) Prep-ing with old (SSC vintage) detectors Readout electronics  Each chip: 1000 x (analog, charge & time digit, calib., serial out)  Preliminary designs complete; need to fill in details; simulate  Conservative: increase channel footprint to 200  m x 500  m

3. 3 Ramp Threshold Ref Logic 8.3 ms 200 ns High Gain Low Gain Shaper VCal Cf Ccal Range Bit Buffered High Range Output Buffered Low Range Output Buffered Timing Signal Common Timing Ramp

4. 4 Inputs from previous Page Common Wilkinson Ramp GeneratorWilkinson Scaler ADC Latch Threshold Latch (For Future zero suppression) Scaler Bus 12 bitsThreshold Timing Signal Output Buffer

5. R Frey 9/15/20035 Si detectors: revised metallization

6. R Frey 9/15/20036 EGS Studies First: An old result 500 GeV electrons SD: 30 x 5/7 X 0 SD vB: 20 x 5/7 X 0 + 10 x 10/7 X 0

7. R Frey 9/15/20037 Geant4 v EGS4 – First Look Total Energy deposited: ← EGS4 (MeV) G4: 4960 ± 40 MeV G4: test beam setup, N. Graf: 30x(W+G10+Si+G10+Cu+air), 5 GeV e- EGS4: same config. Energy dep. in silicon: ← EGS4 (MeV) G4: 66 ± 5 MeV

8. R Frey 9/15/20038 Timeline (highly speculative) 12/03: W and proto-Si in hand & undergoing tests  12/03: readout chip design – complete 1 st iteration Winter 04: characterize detectors; prepare for B-field test  Readout few channels using external electronics Spring 04: have first readout chips in hand Summer 04: contemplate specialized tests in e- test beam  Electronics: heat, power pulsing, showers in chips  Detectors: resolution, noise, calibration Summer 04: Next round of detectors and readout chips  Prepare for full-depth prototype Fall 04: 1 st bump-bonding trials Winter 05: construct full-depth prototype for beam test(s) In parallel, continue with simulations:  Technical: EGS4, G4  Parameter optimizations based on PFlow