1. Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 2 Microcomputer Systems Design (Embedded Systems)

2. VHDL Part 2 2 Content  Process  Signals vs. Variables  Conditional statement  Loops  Sequential & Parallel design  Signals & Modules  Test Bench  Reporting

3. VHDL Part 2 3 Structure of process

4. VHDL Part 2 4 Structure of process

5. VHDL Part 2 5 Structure of process

6. VHDL Part 2 6 Structure of process

7. VHDL Part 2 7 Structure of process

8. VHDL Part 2 8 Process Execution

9. VHDL Part 2 9 Sensitivity list and Signals in a Process

10. VHDL Part 2 10 Sensitivity list and Variables in a Process

11. VHDL Part 2 11 Sensitivity list and Variables in a Process

12. VHDL Part 2 12 Sensitivity list and Variables in a Process

13. VHDL Part 2 13 Signals vs. Variables

14. VHDL Part 2 14 Signals vs. Variables

15. VHDL Part 2 15 Signals vs. Variables

16. VHDL Part 2 16 Controlling the sequence of statements

17. VHDL Part 2 17 Conditional statements

18. VHDL Part 2 18 Conditional statements

19. VHDL Part 2 19 Conditional statements

20. VHDL Part 2 20 Conditional statements with alternatives

21. VHDL Part 2 21 Conditional statements with alternatives

22. VHDL Part 2 22 Multiple Choices

23. VHDL Part 2 23 Multiple Choices

24. VHDL Part 2 24 Loop with a counter

25. VHDL Part 2 25 Loop with a counter

26. VHDL Part 2 26 Loop with a counter

27. VHDL Part 2 27 Loop with a counter

28. VHDL Part 2 28 The world is not sequential.. !!

29. VHDL Part 2 29 How an architecture is executed

30. VHDL Part 2 30 How an architecture is executed

31. VHDL Part 2 31 How an architecture is executed

32. VHDL Part 2 32 How an architecture is executed

33. VHDL Part 2 33 Do you really need a process ?!

34. VHDL Part 2 34 Do you really need a process ?!

35. VHDL Part 2 35 Conditional Signal assignments

36. VHDL Part 2 36 Conditional Signal assignments

37. VHDL Part 2 37 Selected Signal assignment

38. VHDL Part 2 38 Selected Signal assignment

39. VHDL Part 2 39 Signals and modules

40. VHDL Part 2 40 Signals and modules

41. VHDL Part 2 41 Multi-level logic

42. VHDL Part 2 42 Multi-level logic

43. VHDL Part 2 43 Multi-level logic

44. VHDL Part 2 44 Multi-level logic

45. VHDL Part 2 45 Structural design

46. VHDL Part 2 46 Elements of structural descriptions

47. VHDL Part 2 47 Positional port mapping

48. VHDL Part 2 48 Named port association

49. VHDL Part 2 49 Complex port mapping

50. VHDL Part 2 50 Component declaration

51. VHDL Part 2 51 Component instantiation

52. VHDL Part 2 52 Test Bench.. ?!

53. VHDL Part 2 53 VHDL test bench

54. VHDL Part 2 54 Elements of a VHDL test bench

55. VHDL Part 2 55 Elements of a VHDL test bench

56. VHDL Part 2 56 Using test benches

57. VHDL Part 2 57 Using test benches

58. VHDL Part 2 58 Using test benches

59. VHDL Part 2 59 Using test benches

60. VHDL Part 2 60 Unit Under Test

61. VHDL Part 2 61 Unit Under Test

62. VHDL Part 2 62 Unit Under Test

63. VHDL Part 2 63 Unit Under Test

64. VHDL Part 2 64 Stimuli of signals

65. VHDL Part 2 65 Assert statement

66. VHDL Part 2 66 Reporting with assertions

67. VHDL Part 2 67 Summary  Process  Signals vs. Variables  Conditional statement  Loops  Sequential & Parallel design  Signals & Modules  Test Bench  Reporting

68. VHDL Part 2 68 Good luck