1. CMP research colloquiumNovember 5, 2007 Improving Memory Power and Performance for CMPs John Carter Students: Devyani Ghosh Kshitij Sudan Aniruddha Udipi

2. CMP research colloquiumNovember 5, 2007 Scaling the CMP Memory Wall l How should CMP memory hierarchy be organized? –What are the power/perf./reliability/verifiability/cost tradeoffs? –Tiled vs Hierarchical vs. NUCA vs 3-D cache organizations l What resource allocation and caching policies? –How (if at all) should cache be shared? Dynamic vs static. –Is benefit of cooperation sufficient given extra design/verification? l Can we move computation to data? –Caches not always useful; moving data often a waste –Perform “add (x1), #1  r3” wherever (x1) is located l Enhanced coherence protocols –Support for updates, speculative use of data, etc. –Idea: Use machine learning to determine “opt” protocol behavior Devyani Aniruddha Kshitij

3. CMP research colloquiumNovember 5, 2007 Tiled Cache Organization l Cookie-cutter design –N copies of CPU design –Easiest to build/verify/… l Resource sharing? l Interconnect bottleneck? l Memory controllers? l Scalability? L1I CPU 4 L2 L1D Interconnect L1I CPU 5 L2 L1DL1I CPU 6 L2 L1DL1I CPU 7 L2 L1D L1I CPU 0 L2 L1DL1I CPU 1 L2 L1DL1I CPU 2 L2 L1DL1I CPU 3 L2 L1D

4. CMP research colloquiumNovember 5, 2007 Hierarchical Cache Organization l Scalable hierarchy –More complex protocols –Better scaling l Resource sharing? l What hierarchy? l Memory controllers? Interconnect L2 L1I CPU 0 L1DL1I CPU 1 L1DL1I CPU 2 L1DL1I CPU 3 L1D L1I CPU 4 L1DL1I CPU 5 L1DL1I CPU 6 L1DL1I CPU 7 L1D L3 L2

5. CMP research colloquiumNovember 5, 2007 NUCA Cache Organization l Malleable by design –Sea of caches –Islands of CPU –Memory controller atolls? l Static/dynamic allocation of cache  cores –Who needs more capacity? –Which cores cooperating? –Migrate/replicate data 3-D (2.5-D) possible for any design. L1 I $ L1 D $ CPU 2 L1 I $ L1 D $ CPU 3 L1 D $ L1 I $ CPU 7 L1 D $ L1 I $ CPU 6 L1 D $ L1 I $ CPU 1 L1 D $ L1 I $ CPU 0 L1 I $ L1 D $ CPU 4 L1 I $ L1 D $ CPU 5