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S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]
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S. Reda EN160 SP’07 Design Layout using Tanner L-Edit
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S. Reda EN160 SP’07 How can we design the layout for an inverter?
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S. Reda EN160 SP’07 Design Rules
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S. Reda EN160 SP’07 1. First specify λ (using 0.5μ technology)
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S. Reda EN160 SP’07 N well creation
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S. Reda EN160 SP’07 Active region
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S. Reda EN160 SP’07 P-Select
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S. Reda EN160 SP’07 N-select
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S. Reda EN160 SP’07 Active well/substrate taps
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S. Reda EN160 SP’07 Select for taps
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S. Reda EN160 SP’07 Polysilicon
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S. Reda EN160 SP’07 Metal 1
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S. Reda EN160 SP’07 Contacts (to active)
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S. Reda EN160 SP’07 Contacts to poly
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S. Reda EN160 SP’07 Contacts to poly
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S. Reda EN160 SP’07 Little metal1 for input pin
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S. Reda EN160 SP’07 Via1 from metal1 to metal2
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S. Reda EN160 SP’07 Add little metal2 for output pin
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S. Reda EN160 SP’07 Design Rule Checker (DRC) verifies that your layout did not violate any rules ignore these now error
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S. Reda EN160 SP’07 Label your inverter pins
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S. Reda EN160 SP’07 Extract your design into SPICE to simulate and verify it
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S. Reda EN160 SP’07 Verify your inverter DC characteristics in SPICE Fix your SPICE input file first simulate and plot
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