1. Device Sizing Techniques for High Yield Minimum-Energy Subthreshold Circuits Dan Holcomb and Mervin John University of California, Berkeley EE241 Spring 2008

2. Model of Sub-Vt Energy Sub-Vt Operation offers Minimum Energy for low performance systems Theoretical Optimal Vdd can be found from: Variation complicates the design!

3. Impact of Major Design Parameters Optimal Vdd set by relative significance of dynamic and leakage energy – ->but higher Vdd reduces impact of variation Reduced Logic Depth reduces leakage time – ->but longer paths average out delay variability Minimum Sized have lowest C eff – ->but

4. Model of Variation W, L mismatch Vt variation has significant impact on subthreshold circuit functionality

5. Evaluating Failure using SNM Logic levels determine functionality – Challenging in subthreshold NAND-NOR circuit – NAND has most stringent V IH requirement – NOR has most stringent V IL 15mV margin

6. Inferring Gate Failure Rates Monte Carlo SNM analysis has limitations – We infer failure rate from SNM distribution – Good agreement with accepted method

7. Sizing to Minimize Supply Voltage Design Goal – Min Energy with 80% yield at 100k gates Optimal P:N ratio =.5 – Sweep sizing to find maximum SNM Upsizing enables lower voltages – Does low-voltage lead to min-energy?

8. Current and Delay Variability Current and Delay variability decreases with upsizing To meet timing constraints, have to operate circuit at slowest path

9. Conclusions Optimal sizing is highly dependent on loading. – Optimal and stacking can also vary – Upsize according to loading

11. Backup Optimize inner loop SNM calculation

12. Finding P/N Ratio Finding