1. Simulation Interface Final Presentation Guy Zur Eithan Nadir Instructor : Igal Kogan

2. Project Goal: Design and implementation of a generic signal generator for test procedures of DUT (Device Under Test) by using SoPC platform. Design and implementation of a generic signal generator for test procedures of DUT (Device Under Test) by using SoPC platform. Quick Overview:

3. Requirements Receive global parameters from a PC. Receive global parameters from a PC. Processing of the parameters using Embedded 32bit RISC Processor. Processing of the parameters using Embedded 32bit RISC Processor. Design of the unique signal generator controllers. Design of the unique signal generator controllers. Design a feedback module with digital signal processing capabilities. Design a feedback module with digital signal processing capabilities.

4. Virtex II Pro PowerPC 405 Core Logic Cells RAMs Project resources Evaluation Platform Evaluation Platform –XUPV2P FPGA : FPGA : Virtex II Pro platform architecture Processor : Processor : PowerPC 405

5. Working Phases 1.General Tester – CoreGen Controller

6. Working Phases 1.General Tester Transmit time slot data through the Ethernet. Transmit time slot data through the Ethernet. Store it in the ddr, using PPC. Store it in the ddr, using PPC. Extract the data from the ddr DIMM by control_unit ip and deliver it to the DUT. Extract the data from the ddr DIMM by control_unit ip and deliver it to the DUT. A special arbiter decides who has access to the memory. A special arbiter decides who has access to the memory. Memory controller is based on xilinx ’ s MIG. Memory controller is based on xilinx ’ s MIG.

7. Working Phases 1.General Tester – control unit

8. Working Phases 1.General Tester – control unit - internal

9. Working Phases 1.General Tester – dsp unit - internal

10. Working Phases 1.General Tester - Work plan 1. Understanding the DIMM : 1.mimic the data received by the Ethernet  a function that writes to the memory. 2.Implement a DIMM controller using Xilinx CoreGen. 3.Impliment the Arbiter. 4.Simulate the controller with the arbiter. 5.Make a DIMM model to work with the DIMM controller. 6.read this data using hardware interface and write it to the uart. Done √ Fail X

11. Working Phases 1.General Tester - Work plan 2. Impliment the control Unit and test it with the uart. 3. Impliment the Xsga Controller. 1.Understand the VGA interface. 2.Design a debug mode which write a test pattern picture on the screen

12. 2.General Tester – DDR-PLB Controller DDR-PLB Controller

13. Working Phases 2. General Tester – DDR-PLB Controller Changing the strategy above. instead of using a DMA, PPC = DMA controller. Changing the strategy above. instead of using a DMA, PPC = DMA controller. The read fifo of the Control unit produce interrupts- according to these interrupts the system will then fetch the next streaming data from the memory. The read fifo of the Control unit produce interrupts- according to these interrupts the system will then fetch the next streaming data from the memory.

14. Working Phases 2. General Tester – DDR-PLB Controller Built Design

15. Working Phases 2. General Tester – DDR-PLB Controller We assumed that by working with processor clock of 300Mhz, using the 64bit of the plb and reading 16bit@100Mhz, We can produce the proper rate. We assumed that by working with processor clock of 300Mhz, using the 64bit of the plb and reading 16bit@100Mhz, We can produce the proper rate.

16. Working Phases 2. General Tester – DDR-PLB Controller Control Unit

17. Working Phases 2. General Tester – DDR-PLB Controller SVGA CNTRLR

18. Working Phases 2. General Tester – DDR-PLB Controller Simulation We simulated the design in Hdl simulation tool Surprise: The plb uses only the lower 32 bits. Result: We had severe timing problem. We couldn ’ t simulate the interrupt controller, but in general, our control unit seemed to work fine and the special control unit drivers seemed to work properly. We ’ ve enabled user logic address range support, software slave registers and interrupt support. We have spent a great deal of time understanding the IPIF protocol of the above interfaces with the plb_controller.

19. Working Phazes 2. General Tester – DDR-PLB Controller Real Time The above design has been built and compiled On the hard way we discovered that the interrupts are called ALL THE TIME. we are actually in a constant underflow state of the fifo inside the control unit. THIS IS A DESIGN BUG THAT COULDN ’ T BE RESOLVED

20. Working Phazes 2. General Tester – DDR-PLB Controller Real Time Demonstration

21. 3. Transmit a Bitmap Picture Over the Ethernet

22. Working Phases 3. General Tester – Transmit a Bitmap Picture Over the Ethernet

23. Working Phases 3. General Tester – Transmit a Bitmap Picture Over the Ethernet Server and Client Using Xilnet Libs we have developed a server that listens to a specific port. Whenever a client requests the server response and receives data.

24. Working Phases 3. General Tester – Transmit a Bitmap Picture Over the Ethernet We have designed a special FTP protocol. The client transmit size of a file (in bytes), and instantly transmits the file.

25. Working Phases 3. General Tester – Transmit a Bitmap Picture Over the Ethernet PLB tft controller While on the previous phase we used a pure hardware controller, the plb_ftf controller is xilinx ’ s IP designed to write to the xsga controller using the plb. We have written a function that produces test pattern and transmits it to the screen. As well as another function that accesses a memory address (on the ddr – because of the size) and transmits it to the screen.

26. Working Phases 3. General Tester – Transmit a Bitmap Picture Over the Ethernet Demonstration + Bug Explanation

27. 4. Streaming Data Transmission using the Svga controller using the Svga controller

28. Working Phases 4. General Tester – Streaming Data transmitted using the svga controller

29. Working Phases 4. General Tester – Streaming Data transmitted using the svga controller stream Unit

30. Receives data (4BX1KB)from the opb, store it in a DPR 4BX2K. This dpr is divided into two. Once a load command receives the msb of read address is switched. Write clock is opb clk Read clock is screen clk The memory range is divided such that in base address located control registers  test mode/ switch addresses ranges. Base address + 0x10= write data to the dpr. Base address + 0x10= write data to the dpr.

31. Working Phases 4. General Tester – Streaming Data transmitted using the svga controller stream Unit - internal

32. Working Phases 4. General Tester – Streaming Data transmitted using the svga controller Software Accessing the stream unit is divided to two as mentioned above. Lets follow the next example //clearing the control registers XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR, 0x0); //turn test mode on XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR, 0x1); //test mode //switch memory array primary to secondary or vice versa. XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR, 0x2);//load done //clear the req above XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR, 0x0); // clear load

33. Working Phases 4. General Tester – Streaming Data transmitted using the svga controller Software //write pixels data: for(i=0; i< 1024;i++) { //set RGB values r=0xFF; g=0; b=0; pixel=r; pixel= pixel << 8; pixel += g; pixel= pixel << 8; pixel += b; XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR + 0x10+i*4,i); } XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR, 0x2);//load done XIo_Out32(XPAR_STREAM_UNIT_0_AR0_BASEADDR, 0x0); // clear load  STREAM_UNIT_Load ( XPAR_STREAM_UNIT_0_AR0_BASEADDR );

34. Working Phases 4. General Tester – Streaming Data transmitted using the svga controller Demonstration

35. Working Phases General Tester – Streaming Data transmitted using the svga controller Questions ? ? ?

36. F I N