1. Latches Section 4-2 Mano & Kime

2. Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only on current input but also on past input values –Need some type of memory to remember the past input values

3. Circuits that we have learned so far Information Storing Circuits Timed “States”

4. Storing Information Buffers Inverters

5. Can’t change the stored value!

6. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand

7. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand

8. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand

9. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set

10. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store

11. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store

12. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store

13. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 0 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset

14. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset

15. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0

16. !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0

17. S-R Latches

19. fb1 fb2

20. S-R Latch Simulation

21. S - R Latch with a Clock Signal (Sequential)

22. S-R Latch !S !R Q !Q S R CLK S R CLK !S !R Q !Q 0 0 1 1 1 Q 0 !Q 0 Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q 0 !Q 0 Store

24. D Latch Q !Q CLK D !S !R S R S R CLK Q !Q 0 0 1 Q 0 !Q 0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 !Q 0 Store 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q

25. D Latch Q !Q CLK D !S !R S R 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

26. D Latch CLK D Q E x y z x y z Does NOT latch z = z $ x = 0 $ 1 = 1 Latches on following edge of clock

27. D Latch CLK D Q E x y z x y z Does latch z = z $ x = 0 $ 1 = 1 Use narrow pulse If x remains high, successive clock pulses will toggle z

28. D Latch with Transmission Gates