1. Performed by: Kazarinov Yair Instructor: Inna Rivkin
Final Project Report
Performed by:
Kazarinov Yair
Instructor:
Inna Rivkin

2. Project: MICROPROCESSOR DESIGN & IMPLEMENTATION

3. Project Goal
Architectural definition, implementation and testing of general-purpose microprocessor which is able to run basic machine language.

4. Project Goal - cont.
The microprocessor is implemented in VHDL using design tools MENTOR GRAPHICS and ALTERA :
RENOIR for VHDL design
MODELSIM for design simulation
LEONARDO for synthesis
MAXPLUS2 for place and route

5. Architecture Description
The microprocessor has 16-bit RISK instruction set architecture:
8 general purpose registers,
register size 2 bytes
16 bit data path width
instruction length is 2 bytes

6. Architecture Description - cont.
The microprocessor supports 1MB memory addressing – 20-bit address bus. Special registers define 4 bits of address base:
CR – Code segment
SR – Stack segment
DR – Data segment
IR – Interrupt routines segment

7. DMA requests / design test logic
System Diagram
CPU/DMA
request control
DMA requests / design test logic
Control / interrupt /
FPGA CPU
Main
Memory /
DMA source
block
Control
signals
CPU Read/write
data
Interrupt
vector 8
DMA data bus 16
CPU / DMA source addr. 8
Test
data 20
DMA
request control
DMA
destination
memory block 20
DMA
source &
destination
addresses
DMA dest.
address 20

8. Architecture Description - cont.
Supported instructions are divided into the following categories:
ALU instructions
Conditional / non-conditional branches
Memory/ stack instructions
Memory segment register load

9. Architecture Description - cont.
Instruction format:
bits [15:11] - instruction opcode
bits [10:8] - destination register
bits [7:0] - source register /
immediate value

10. Architecture Description - cont.
Arithmetic/ logic instructions
ADD (register to register )
ADDI (immediate to register )
SUB (register from register )
SUBI (immediate from register )

11. Architecture Description - cont.
Arithmetic/ logic instructions - cont.
SHL (register shift left )
SHR (register shift right )
ROTL (register rotate left )
ROTR (register rotate right )

12. Architecture Description - cont.
Arithmetic/ logic instructions - cont.
MOV (register to register)
MOVL (immediate to register - low byte)
MOVH (immediate to register - high byte)

13. Architecture Description - cont.
Arithmetic/ logic instructions - cont.
AND (register with register)
ANDL (immediate with register - low byte)
ANDH (immediate with register - high byte)

14. Architecture Description - cont.
Arithmetic/ logic instructions - cont.
NOT (register)
NOTL (register - low byte)
NOTH (register - high byte)

15. Architecture Description - cont.
Arithmetic/ logic instructions - cont.
OR (register with register)
Instructions setting the flags
if register value is positive - set flag POS
if register value zero - set flag ZERO
TST (test signed register operand)
TSTUNS (test unsigned register operand

16. Architecture Description - cont.
Branch instructions
JMP (unconditional direct branch)
JZ (jump if register tested is zero)
JG (jump if tested tested is positive)
JL (jump if tested tested is negative)

17. Architecture Description - cont.
Memory instructions
LOAD (load from memory)
STORE (store register to memory)
PUSH
POP

18. Architecture Description - cont.
Special instructions
LOADREG - load base register
IRET - return from interrupt handler
HALT - processor halt
NOP - no operation

19. Microprocessor interface
Control / interrupt / test inputs
CLK - main clock
RST - processor reset
INT - external interrupt
DATAOUTSEL[3:0] -
Mux select for reading general purpose registers out (either low or high byte of one of 8 registers)

20. Microprocessor interface - cont.
Control / interrupt / test inputs - cont.
DFTMODE design test mode is active
DFTSEL[5:0] -
select signal test trace on test mode

21. Microprocessor interface - cont.
Control / interrupt / test outputs
INTA - external interrupt execution indication
HALT - processor finished execution
DATAOUT[7:0] - general purpose register byte data out -
selected by DATAOUTSEL[3:0]

22. Microprocessor interface - cont.
Control / interrupt / test signals - cont.
IOBUS[7:0] -
Input in regular mode –
interrupt number indication
Output on test mode –
signal trace selected by DFTSEL[5:0]

23. Microprocessor interface - cont.
Outputs to the main memory
REQ -
Main memory request active
ADDR [19:0] -
CPU main memory request address / DMA source address
WxR - Main memory request write(‘0’) / read(‘1’) indication

24. Microprocessor interface - cont.
Inputs from the main memory
RDY - read data valid or write data taken on next cycle

25. Microprocessor interface - cont.
DMA control inputs
DMAREQ - DMA transfer request
DMAADDR[19:0] -
DMA transfer read address (source)
DMATRNSADDR[19:0] -
DMA transfer write address (dest.)
DMATRNSCNT[9:0] -
DMA transfer byte count

26. Microprocessor interface - cont.
DMA control outputs
DMAACT DMA transfer is activated

27. Microprocessor interface - cont.
DMA transfer outputs
to the memory system
TRNSREQ - DMA transfer request
TRNSADDR[19:0] -
DMA destination address
*** source is given by ADDR[19:0]

28. Microprocessor interface - cont.
DMA transfer inputs
from the memory system
DMAACK - performing DMA transfer of requested byte

29. Interrupts
The microprocessor is able to receive external interrupt indication, which is followed by executing of appropriate interrupt handler.
Interrupt number (1 of 256) is being received externally by CPU on 8-bit bus and defines the interrupt vector.

30. DMA transfer
DMA transfer mechanism is able to receive external requests of DMA transfer, which is arbitrated together with CPU memory accesses.
DMA mechanism is to transfer given amount of data from certain location in main memory to the certain location in additional periphery memory block on the external data bus without CPU involvement.

31. Design For Testing
Special testing design is inserted for tracing internal design signals (64 groups of 8 bits) on external bus that can be sampled by logic analyzer.
General-purpose registers are visible on external dedicated output bus.

32. Microarchitecture
The design is divided into two main functional units:
Core Unit - instruction fetch, execution, data read/ write request generation;
Memory Controller
- arbitration of instruction fetch, data read/write requests to the main memory;
- DMA transfer requests handling;

33. Microarchitecture - cont.
Core Unit contains 3 blocks:
Instruction fetch
Instruction decoding / execution
Memory write buffer

34. Microprocessor Block Diagram
Control logic
Execution
Block
Instruction
Fetch
Block
Memory /
DMA
Controller
Control /
Data Path
To Memory
System
Memory
Write
Buffer
Control /
Data Path
Control /
Data Path

35. Microarchitecture - Fetch Block
The block is responsible for getting instruction stream data from the Memory Unit and sending the instructions down the pipe to the execution.
Request protocol supports two concurrent fetch requests pending to the Memory Unit.

36. Fetch Block - cont.
Fetched instructions are accumulated in the instruction buffer with the depth of 4, so instruction fetch and execution are completely independent.

37. Fetch Block - cont.
When the execution block detects either taken branch, CR (code segment) load or valid HALT instruction, it sends flush indication to the fetch block, providing it with the PC of the next instruction where the fetch must start.
The fetch FSM then flushes its internal state and resumes instruction fetch from the given PC.

38. Fetch Block - cont.
Under optimal conditions – when the Memory unit is able to supply one instruction per clock (cache hit), and the execution block finishes one instruction each cycle - CPI is equal 1.

39. Execution Block
The block starts executing the instruction when it recognizes valid instruction coming from the Fetch block.
On the last cycle of instruction execution it asserts EXECDONE signal so that the fetch block can flush the instruction from the buffer and deliver next instruction.

40. Execution Block - cont.
In the best case, the instruction execution is performed during one cycle. It includes all arithmetic / logic / flag test instructions, not taken branches. It does not include memory reference instructions, interrupt handling and special instructions such as LOADREG CR and HALT.

41. Execution Block - cont.
In case of memory read instruction, the ”snoop” is performed to the Write Buffer (4-entry deep store data buffer). In case of miss, data read request is asserted to the Memory unit.
The execution is completed when the data is returned and written to the destination register.

42. Execution Block - cont.
In case of memory write instruction, write request is asserted to the Write Buffer. The execution is completed once the Write Buffer acknowledges the request.

43. Execution Block - cont.
The block also handles interrupt requests.

44. Write Buffer Can hold up to 4 pending write requests.
When at least one entry in the buffer is valid, the block asserts write request to the Memory unit.

45. Memory Controller
Memory control block is a arbiter state machine that get three types of CORE memory requests and DMA request, arbitrates and sends the request to the main memory.

46. Memory Controller The requests that are handled are:
DMA transfer requests (highest priority)
Data read requests from the Execution
Fetch requests from the Fetch block
Write requests from the Write Buffer

47. Memory Controller
The block contains also small instruction cache array with byte entries.
The array is direct mapped, with line size = 2 bytes (single instruction).

48. Logic Validation
The processor’s logic was validated using directed tests to examine various design aspects.
Separated VHDL test module is available that allows easy test writing and compiling. Several test examples are available.

49. Some Wave Forms... Here are two simulation wave forms:
Loop example (cache miss and hits).
Simple DMA transfer sequence.

52. Synthesis Results
The tools for synthesis and P&R to available Altera device are supplied by Mentor Graphics.
Because of design complexity (mainly, instructions complexity) current maximal frequency achieved after all timing optimizations is 25 MHz.
It is recommended to synthesize with 33MHz constraint.

53. Summary
The microprocessor was intended to be physically implemented and executed.
However, due to several limitations, only logic design was implemented and tested.

54. Summary - cont.
Implementation work can be proceeded. The processor designed so that each functional block (fetch, execution, write buffer block, memory controller) works independently and so may be optimized (for example, caches in memory controller, larger instruction set to be executed).

55. End of Presentation… Thank you!