1. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage IX: March 30 th 2004 CHIP LEVEL SIMULATION Presentation #9: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

2. Status  Design Proposal (Done)  Architecture Proposal (Done)  Size Estimates/Floorplan (Done)  Gate Level Design (Done)  Schematic Design (Fixed)  Input/Output Logic to SBOX Changed and Tested  Top Level Schematic Verified – Pipeline Works!  Layout  Component Layout (Done—Continually Changing)  Component Simulations  Chip Level Layout – LVS (Done)  To be Done  SPICE simulation of chip (Not Yet…)  Optimizations  Everything else… 18-525 Integrated Circuit Design Project

3. Status What needed to be done?  Global Routing  Everything is wired internally, needs to be globally connected  Slow and Fast Clock Routing  Select Line Routing  Vdd and Gnd Routing Why wasn’t it done?  LVS  We had problems routing global VDD and clock  Fixed, but still doesn’t LVS  The Outside (Donut) and the Inside (Donut Hole) LVS’ed separately  LVS Options  Had ‘ReWiring’ checked, not sure how this affected previous LVSing  New Schematic created – Closer to how we’re LVSing  Bottom ROM’s output wires were switched when put into DFFs 18-525 Integrated Circuit Design Project

4. Top Level Schematic DFFs for Valid Out Add Round Key Clock Divider Round Permutations and Pipeline DFFs Key Expands and Pipeline DFFs Mux Tree In Mux Tree Out Mux Tree In Mux Tree Out Final Text Out Final Text DFFs Input DFFs Select Logic

5. Verilog Re-Verification 18-525 Integrated Circuit Design Project reg [4:0] counterx; always #5 clk = ~clk; initial begin counterx = 0; end always@(posedge clk) begin counterx = counterx + 1; if (counterx == 21) begin counterx = 0; end end initial begin clk = 1'b1; rst = 1'b1; #10 rst = 1'b0; #10 rst =1; @(posedge valid_in); text_in1[31:0] = 32'h00000000; // Expected: 1B3E9EDF key1[31:0] = 32'hFB473859; vin = 1; @(posedge valid_in); key1[31:0] = 32'b00000000000000000000000000000000; text_in1[31:0] = 32'h08f273e6; // Expected: 2DF5C18E vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h10174E72; // Expected: 87FE42E7 vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h30C42168; // Expected: 0BD9AFAC vin = 1; @(posedge valid_in); key1[31:0] = 32'h2F764A41; text_in1[31:0] = 32'h00000000; // Expected: 43B28B72 vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h91f0aca1; // Expected: c913f5ed vin = 1; @(posedge valid_in); key1[31:0] = 32'h851b64d9; text_in1[31:0] = 32'h00000000; // Expected: 30d0299b vin = 1; @(posedge valid_in); key1[31:0] = 32'hc0000000; text_in1[31:0] = 32'h00000000; // Expected: ec4b0b60 vin = 1; @(posedge valid_in); key1[31:0] = 32'hfff80000; text_in1[31:0] = 32'h00000000; // Expected: b3adb97e vin = 1; @(posedge valid_in); key1[31:0] = 32'h00000000; text_in1[31:0] = 32'h9b0cb284; // Expected: 69551ee1 vin = 1; #10000 $finish; end The Result of the Non-Resetting DFFs (Used to be junk values)

6. LVS

7. Top Level Schematic

8. Current Floorplan 350 um x 335 um Metal 3 Metal 2 Metal 1 Metal 4 SBOX and Control Logic Text DFFs and Add Round Key 5 th Round Key Expand Input to SBOX Logic & Select Output and Input Logic 4 Rounds of Key Expand 4 Rounds of Round Permutation Input/Output Logic CLK Divider Select & Input Logic SBOX and Control Logic Final Text Out Key DFFs and Input Logic

9. POLY AND ACTIVE

10. METAL 1

11. METAL 2

12. METAL 3

13. METAL 4

14. LVS – Donut Area – ROM and Input Logic and Output DFFs 11,992 Transistors

15. LVS – Inner Area – AES Key Expand – All 4 stages 12,922 Transistors

16. Full Layout

17. Final Dimensions Total Area: 350 um x 335 um = 117250 sq. um Transistor Count: 25,204 transistors Transistor Density: 0.215 Aspect Ratio: 1.045 Estimated Clock Speed: 400MHz

18. Questions? 18-525 Integrated Circuit Design Project