1. ELEN 468 Lecture 91 ELEN 468 Advanced Logic Design Lecture 9 Behavioral Descriptions III

2. ELEN 468 Lecture 92 Activity Flow Control ( if … else ) if ( A == B ) P = d; if ( B < C ); if ( a >= b ) begin … end if ( A < B ) P = d; else P = k; if ( A > B ) P = d; else if ( A < B ) P = k; else P = Q; if ( A == B ) P = d; if ( B < C ); if ( a >= b ) begin … end if ( A < B ) P = d; else P = k; if ( A > B ) P = d; else if ( A < B ) P = k; else P = Q; Syntax: if ( expression ) statement [ else statement ] Value of expression 0, x or z => false Non-zero number => true

3. ELEN 468 Lecture 93 Conditional Operator ( ? … : ) always @ ( posedge clock ) yout = ( sel ) ? a + b : a – b; always @ ( posedge clock ) yout = ( sel ) ? a + b : a – b; Conditional operator can be applied in either continuous assignments or behavioral descriptions

4. ELEN 468 Lecture 94 The case Statement module mux4 ( a, b, c, d, select, yout ); input a, b, c, d; input [1:0] select; output yout; reg yout; always @( a or b or c or d or select ) begin case ( select ) 0: yout = a; 1: yout = b; 2: yout = c; 3: yout = d; default yout = 1`bx; endcase endmodule module mux4 ( a, b, c, d, select, yout ); input a, b, c, d; input [1:0] select; output yout; reg yout; always @( a or b or c or d or select ) begin case ( select ) 0: yout = a; 1: yout = b; 2: yout = c; 3: yout = d; default yout = 1`bx; endcase endmodule Case items are examined in order Exact match between case expression and case item casex – don’t care bits with x or z casez – don’t care bits with z

5. ELEN 468 Lecture 95 Expression Matching in case Construct always @ ( pulse ) casez ( word ) 8`b0000???? : ; … always @ ( pulse ) casez ( word ) 8`b0000???? : ; … Expression or case_item casecasexcasez 0000 1111 xx0 1 x zx zz ?N/A 0 1 x z

6. ELEN 468 Lecture 96 Loops repeat for loop while loop forever disable

7. ELEN 468 Lecture 97 The repeat Loop … word_address = 0; repeat ( memory_size ) begin memory [word_address] = 0; word_address = word_address + 1; end … word_address = 0; repeat ( memory_size ) begin memory [word_address] = 0; word_address = word_address + 1; end …

8. ELEN 468 Lecture 98 The for Loop reg [15:0] regA; integer k; … for ( k = 4; k; k = k – 1 ) begin regA [ k+10 ] = 0; regA [ k+2 ] = 1; end … reg [15:0] regA; integer k; … for ( k = 4; k; k = k – 1 ) begin regA [ k+10 ] = 0; regA [ k+2 ] = 1; end … Loop variables have to be either integer or reg

9. ELEN 468 Lecture 99 The while Loop begin cnt1s reg [7:0] tmp; cnt = 0; tmp = regA; while ( tmp ) begin cnt = cnt + tmp[0]; tmp = tmp >> 1; end begin cnt1s reg [7:0] tmp; cnt = 0; tmp = regA; while ( tmp ) begin cnt = cnt + tmp[0]; tmp = tmp >> 1; end module sth ( externalSig ); input externalSig; always begin while ( externalSig ); end endmodule module sth ( externalSig ); input externalSig; always begin while ( externalSig ); end endmodule Loop activities suspend external activities Replacement for while ?

10. ELEN 468 Lecture 910 The disable Statement begin k = 0; for ( k = 0; k <= 15; k = k + 1 ) if ( word[ k ] == 1 ) disable ; end begin k = 0; for ( k = 0; k <= 15; k = k + 1 ) if ( word[ k ] == 1 ) disable ; end Terminate prematurely in a block of procedural statements

11. ELEN 468 Lecture 911 The forever Loop parameter half_cycle = 50; initial begin : clock_loop clock = 0; forever begin #half_cycle clock = 1; #half_cycle clock = 0; end initial #350 disable clock_loop; parameter half_cycle = 50; initial begin : clock_loop clock = 0; forever begin #half_cycle clock = 1; #half_cycle clock = 0; end initial #350 disable clock_loop;

12. ELEN 468 Lecture 912 “always” and “forever” alwaysforever Declares a behaviorComputational activity flow within a behavior Cannot be nestedCan be nested Executes when simulation begins Executes when statement is reached

13. ELEN 468 Lecture 913 Parallel Activity Flow … fork // t_sim = 0 #50 wave = 1; #100 wave = 0; #150 wave = 1; #300 wave = 0; // executes at t_sim = 300 join … fork // t_sim = 0 #50 wave = 1; #100 wave = 0; #150 wave = 1; #300 wave = 0; // executes at t_sim = 300 join … module race ( … ); … fork #150 a = b; #150 c = a; join endmodule module fix_race ( … ); … fork a = #150 b; c = #150 a; join endmodule module race ( … ); … fork #150 a = b; #150 c = a; join endmodule module fix_race ( … ); … fork a = #150 b; c = #150 a; join endmodule Not supported by synthesis For simulation in testbench

14. ELEN 468 Lecture 914 Tasks and Functions Sub-programs that encapsulate and organize a description Tasks – create a hierarchical organization of the procedural statements Functions – substitute for an expression

15. ELEN 468 Lecture 915 Tasks Declared within a module Referenced in a behavior In module where the task is declared From any module through hierarchical de-referencing All arguments to the task are passed by value, not pointer Parameters can be passed to a task, variables and parameters within the parent module of a task are visible to the task A task may not be used within an expression Statements in a task may contain delay and event control A task can call itself

16. ELEN 468 Lecture 916 Example of Task module bit_counter (data, count); input [7:0] data; output [3:0] count; reg [3:0] count; always @(data) t(data, count); task t; input [7:0] a; output [3:0] c; reg [3:0] c; reg [7:0] tmp; begin c = 0; tmp = a; while (tmp) begin c = c + tmp[0]; tmp = tmp >> 1; end endtask endmodule module bit_counter (data, count); input [7:0] data; output [3:0] count; reg [3:0] count; always @(data) t(data, count); task t; input [7:0] a; output [3:0] c; reg [3:0] c; reg [7:0] tmp; begin c = 0; tmp = a; while (tmp) begin c = c + tmp[0]; tmp = tmp >> 1; end endtask endmodule

17. ELEN 468 Lecture 917 Functions Implement only combinational behavior Compute and return a value for given parameters Have no timing/event control May call other functions, not itself Can be referenced anywhere an expression can exist May not declare any output or inout port Must have at least one input port

18. ELEN 468 Lecture 918 Example of Function module word_aligner (w_in, w_out); input [7:0] w_in; output [7:0] w_out; assign w_out = align (w_in); function [7:0] align; input [7:0] word; begin align = word; if (align != 0) while (align[7] == 0) align = align << 1; end endfunction endmodule module word_aligner (w_in, w_out); input [7:0] w_in; output [7:0] w_out; assign w_out = align (w_in); function [7:0] align; input [7:0] word; begin align = word; if (align != 0) while (align[7] == 0) align = align << 1; end endfunction endmodule

19. ELEN 468 Lecture 919 Static vs. Dynamic Timing Analysis Static timing analysis Fast Consider all paths Pessimism by considering false paths which are never exercised Dynamic timing analysis ( simulation ) Depends on input stimulus vectors Do not report timing on false paths With large number of testing vectors  Accurate  Slow

20. ELEN 468 Lecture 920 Example of Static Timing Analysis Arrival time: input -> output, take max Required arrival time: output -> input, take min Slack = required arrival time – arrival time 2 3 4 3 7 11 2 3 7/4/-3 5/3/-2 4/7/34/7/3 8/8/08/8/0 9/6/-3 20/17/-3 11/11/0 18/18/0 23/20/-3

21. ELEN 468 Lecture 921 Setup Time Constraint $setup(data, posedge clock, 5); It specifies an interval before the active edge of clock Data must arrive before the interval 5 5 clock data

22. ELEN 468 Lecture 922 Hold Time Constraint $hold(data, posedge clock, 2); It specifies an interval after the active edge of clock Data must be stable in the interval 2 2 clock data

23. ELEN 468 Lecture 923 Setup and Hold Time $setuphold(data, posedge clock, 5, 2); 5 5 clock data 22

24. ELEN 468 Lecture 924 Signal Period $period(posedge clock, t_limit); Signal period must be sufficiently long clock t_limit clock cycle time

25. ELEN 468 Lecture 925 Pulse Width $width(posedge clock, t_mpw); The width of the clock pulse must not be too small clock t_mpw clock pulse width

26. ELEN 468 Lecture 926 Clock Skew $skew(negedge clk1, negedge clk2, t_skew); Signal skew is the arriving time difference of two clock signals Clock skew should be limited clk1 clk2 skew

27. ELEN 468 Lecture 927 Bus_control Recovery Time $recovery(negedge bus_control, bus_driver, t_rec); Time to go from Z to 0 or 1 Bus_driver t_rec Z

28. ELEN 468 Lecture 928 No Signal Change $nochange(posedge clk, data, -5, 2); Equivalent to $setuphold(data, posedge clk, 5, 2);

29. ELEN 468 Lecture 929 Finer-grain and Conditional Events Timing Check $setup ( data, edge 01 clk, 5 ); $hold ( data, edge 10 clk, 2 ); $setup ( data, posedge clk &&& (!reset), 4 ); $setup ( data, edge 01 clk, 5 ); $hold ( data, edge 10 clk, 2 ); $setup ( data, posedge clk &&& (!reset), 4 );

30. ELEN 468 Lecture 930 De-Reference To reference a variable defined inside a behavioral block X.Y.k module X( … ); end begin : Y reg k; … end