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ceg3420 control.1 ©UCB, DAP’ 97 CEG3420 Computer Design Lecture 9.2: Designing Single Cycle Control
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ceg3420 control.2 ©UCB, DAP’ 97 Recap: Summary from last time °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °MIPS makes it easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates °Single cycle datapath => CPI=1, CCT => long °Next time: implementing control
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ceg3420 control.3 ©UCB, DAP’ 97 Recap: The MIPS Instruction Formats °All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type °The different fields are: op: operation of the instruction rs, rt, rd: the source and destination registers specifier shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits
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ceg3420 control.4 ©UCB, DAP’ 97 Recap: The MIPS Subset °ADD and subtract add rd, rs, rt sub rd, rs, rt °OR Imm: ori rt, rs, imm16 °LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 °BRANCH: beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits
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ceg3420 control.5 ©UCB, DAP’ 97 Recap: A Single Cycle Datapath °We have everything except control signals (underline) Today’s lecture will show you how to generate the control signals
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ceg3420 control.6 ©UCB, DAP’ 97 The Big Picture: Where are We Now? °The Five Classic Components of a Computer °Today’s Topic: Designing the Control for the Single Cycle Datapath Control Datapath Memory Processor Input Output
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ceg3420 control.7 ©UCB, DAP’ 97 Outline of Today’s Lecture °Recap and Introduction (10 minutes) °Control for Register-Register & Or Immediate instructions (10 minutes) °Questions and Administrative Matters (5 minutes) °Control signals for Load, Store, Branch, & Jump (15 minutes) °Building a local controller: ALU Control (10 minutes) °Break (5 minutes) °The main controller (20 minutes) °Summary (5 minutes)
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ceg3420 control.8 ©UCB, DAP’ 97 RTL: The Add Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits
![ceg3420 control.8 ©UCB, DAP’ 97 RTL: The Add Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits](http://images.slideplayer.com./16/5031632/slides/slide_8.jpg "ceg3420 control.8 ©UCB, DAP’ 97 RTL: The Add Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits")
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ceg3420 control.9 ©UCB, DAP’ 97 Instruction Fetch Unit at the Beginning of Add PC Ext °Fetch the instruction from Instruction memory: Instruction <- mem[PC] This is the same for all instructions Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction
![ceg3420 control.9 ©UCB, DAP’ 97 Instruction Fetch Unit at the Beginning of Add PC Ext °Fetch the instruction from Instruction memory: Instruction <- mem[PC] This is the same for all instructions Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction](http://images.slideplayer.com./16/5031632/slides/slide_9.jpg "ceg3420 control.9 ©UCB, DAP’ 97 Instruction Fetch Unit at the Beginning of Add PC Ext °Fetch the instruction from Instruction memory: Instruction <- mem[PC] This is the same for all instructions Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction")
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ceg3420 control.10 ©UCB, DAP’ 97 The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 1 Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rd] <- R[rs] + R[rt] 0 1 0 1 01 Imm16RdRsRt oprsrtrdshamtfunct 061116212631 nPC_sel= +4
![ceg3420 control.10 ©UCB, DAP’ 97 The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 1 Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rd] <- R[rs] + R[rt] Imm16RdRsRt oprsrtrdshamtfunct nPC_sel= +4](http://images.slideplayer.com./16/5031632/slides/slide_10.jpg "ceg3420 control.10 ©UCB, DAP’ 97 The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 1 Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rd] <- R[rs] + R[rt] Imm16RdRsRt oprsrtrdshamtfunct nPC_sel= +4")
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ceg3420 control.11 ©UCB, DAP’ 97 Instruction Fetch Unit at the End of Add °PC <- PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction
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ceg3420 control.12 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate °R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate 016212631 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = Extender Mux 32 16 imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel =
![ceg3420 control.12 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate °R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =](http://images.slideplayer.com./16/5031632/slides/slide_12.jpg "ceg3420 control.12 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate °R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =")
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ceg3420 control.13 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rt] <- R[rs] or ZeroExt[Imm16] 0 1 0 1 01 Imm16RdRsRt oprsrtimmediate 016212631 nPC_sel= +4
![ceg3420 control.13 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rt] <- R[rs] or ZeroExt[Imm16] Imm16RdRsRt oprsrtimmediate nPC_sel= +4](http://images.slideplayer.com./16/5031632/slides/slide_13.jpg "ceg3420 control.13 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rt] <- R[rs] or ZeroExt[Imm16] Imm16RdRsRt oprsrtimmediate nPC_sel= +4")
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ceg3420 control.14 ©UCB, DAP’ 97 Questions and Administrative Matters °Midterm next Wednesday 10/8/97: 5:30pm to 8:30pm, 306 Soda No class on that day °Midterm reminders: Pencil, calculator, two 8.5” x 11” pages of handwritten notes Sit in every other chair, every other row (odd row & odd seat) °Meet at LaVal’s pizza after the midterm -Need a headcount. How many are definitely coming?
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ceg3420 control.15 ©UCB, DAP’ 97 The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate 016212631 nPC_sel= +4
![ceg3420 control.15 ©UCB, DAP’ 97 The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate nPC_sel= +4](http://images.slideplayer.com./16/5031632/slides/slide_15.jpg "ceg3420 control.15 ©UCB, DAP’ 97 The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate nPC_sel= +4")
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ceg3420 control.16 ©UCB, DAP’ 97 The Single Cycle Datapath during Store °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = Extender Mux 32 16 imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel =
![ceg3420 control.16 ©UCB, DAP’ 97 The Single Cycle Datapath during Store °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =](http://images.slideplayer.com./16/5031632/slides/slide_16.jpg "ceg3420 control.16 ©UCB, DAP’ 97 The Single Cycle Datapath during Store °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =")
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ceg3420 control.17 ©UCB, DAP’ 97 The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631 nPC_sel= +4
![ceg3420 control.17 ©UCB, DAP’ 97 The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate nPC_sel= +4](http://images.slideplayer.com./16/5031632/slides/slide_17.jpg "ceg3420 control.17 ©UCB, DAP’ 97 The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate nPC_sel= +4")
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ceg3420 control.18 ©UCB, DAP’ 97 The Single Cycle Datapath during Branch 32 ALUctr = Subtract Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate 016212631 nPC_sel= “Br”
![ceg3420 control.18 ©UCB, DAP’ 97 The Single Cycle Datapath during Branch 32 ALUctr = Subtract Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate nPC_sel= Br](http://images.slideplayer.com./16/5031632/slides/slide_18.jpg "ceg3420 control.18 ©UCB, DAP’ 97 The Single Cycle Datapath during Branch 32 ALUctr = Subtract Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate nPC_sel= Br")
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ceg3420 control.19 ©UCB, DAP’ 97 Instruction Fetch Unit at the End of Branch °if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate 016212631 Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction
![ceg3420 control.19 ©UCB, DAP’ 97 Instruction Fetch Unit at the End of Branch °if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction](http://images.slideplayer.com./16/5031632/slides/slide_19.jpg "ceg3420 control.19 ©UCB, DAP’ 97 Instruction Fetch Unit at the End of Branch °if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction")
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ceg3420 control.20 ©UCB, DAP’ 97 Step 4: Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr
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ceg3420 control.21 ©UCB, DAP’ 97 A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”
![ceg3420 control.21 ©UCB, DAP’ 97 A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = add , RegDst = rd, RegWr, nPC_sel = +4 SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = sub , RegDst = rd, RegWr, nPC_sel = +4 ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = Z , ALUctr = or , RegDst = rt, RegWr, nPC_sel = +4 LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = Sn , ALUctr = add , MemtoReg, RegDst = rt, RegWr, nPC_sel = +4 STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = Sn , ALUctr = add , MemWr, nPC_sel = +4 BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = Br , ALUctr = sub](http://images.slideplayer.com./16/5031632/slides/slide_21.jpg "ceg3420 control.21 ©UCB, DAP’ 97 A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = add , RegDst = rd, RegWr, nPC_sel = +4 SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = sub , RegDst = rd, RegWr, nPC_sel = +4 ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = Z , ALUctr = or , RegDst = rt, RegWr, nPC_sel = +4 LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = Sn , ALUctr = add , MemtoReg, RegDst = rt, RegWr, nPC_sel = +4 STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = Sn , ALUctr = add , MemWr, nPC_sel = +4 BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = Br , ALUctr = sub")
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ceg3420 control.22 ©UCB, DAP’ 97 A Summary of the Control Signals addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtract 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx optarget address oprsrtrdshamtfunct 061116212631 oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op00 0000 00 110110 001110 101100 010000 0010 Appendix A 10 0000See10 0010We Don’t Care :-)
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ceg3420 control.23 ©UCB, DAP’ 97 The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU
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ceg3420 control.24 ©UCB, DAP’ 97 The Encoding of ALUop °In this exercise, ALUop has to be 2 bits wide to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, and (4) Subtract °To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) Main Control op 6 ALU Control (Local) funcN 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx
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ceg3420 control.25 ©UCB, DAP’ 97 The Decoding of the “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct 061116212631 R-type funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 Add Subtract And Or Set-on-less-than Recall ALU Homework (also P. 286 text): ALUctr ALU
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ceg3420 control.26 ©UCB, DAP’ 97 The Truth Table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop 1 000 100 00 0 01 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than
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ceg3420 control.27 ©UCB, DAP’ 97 Break (5 Minutes)
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ceg3420 control.28 ©UCB, DAP’ 97 The Logic Equation for ALUctr ALUopfunc bit ALUctr 0x1xxxx1 1xx00101 1xx10101 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func This makes func a don’t care
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ceg3420 control.29 ©UCB, DAP’ 97 The Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx00001 1xx00101 1xx10101 °ALUctr = !ALUop & !ALUop + ALUop & !func & !func
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ceg3420 control.30 ©UCB, DAP’ 97 The Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx01011 1xx10101 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func
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ceg3420 control.31 ©UCB, DAP’ 97 The ALU Control Block ALU Control (Local) func 3 6 ALUop ALUctr 3 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func °ALUctr = !ALUop & !ALUop + ALUop & !func & !func °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func
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ceg3420 control.32 ©UCB, DAP’ 97 Step 5: Logic for each control signal °nPC_sel <= if (OP == BEQ) then EQUAL else 0 °ALUsrc <=if (OP == “Rtype”) then “regB” else “immed” °ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” °ExtOp <= _____________ °MemWr<= _____________ °MemtoReg<= _____________ °RegWr:<=_____________ °RegDst:<= _____________
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ceg3420 control.33 ©UCB, DAP’ 97 Step 5: Logic for each control signal °nPC_sel <= if (OP == BEQ) then EQUAL else 0 °ALUsrc <=if (OP == “Rtype”) then “regB” else “immed” °ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” °ExtOp <= if (OP == ORi) then “zero” else “sign” °MemWr<= (OP == Store) °MemtoReg<= (OP == Load) °RegWr:<= if ((OP == Store) || (OP == BEQ)) then 0 else 1 °RegDst:<= if ((OP == Load) || (OP == ORi)) then 0 else 1
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ceg3420 control.34 ©UCB, DAP’ 97 The “Truth Table” for the Main Control R-typeorilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) 1 0 0 1 0 0 0 x “R-type” 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx op00 000000 110110 001110 101100 010000 0010 ALUop 1000 0 x 0100 0 x 0000 1 x Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3RegDst ALUSrc :
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ceg3420 control.35 ©UCB, DAP’ 97 The “Truth Table” for RegWrite R-typeorilwswbeqjump RegWrite111000 op00 000000 110110 001110 101100 010000 0010 °RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite
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ceg3420 control.36 ©UCB, DAP’ 97 PLA Implementation of the Main Control RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop
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ceg3420 control.37 ©UCB, DAP’ 97 A Real MIPS Datapath (CNS T0)
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ceg3420 control.38 ©UCB, DAP’ 97 Putting it All Together: A Single Cycle Processor 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr nPC_sel
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ceg3420 control.39 ©UCB, DAP’ 97 Worst Case Timing (Load) Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memoey Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRegOld ValueNew Value AddressOld ValueNew Value busWOld ValueNew Delay through Extender & Mux Register Write Occurs Data Memory Access Time
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ceg3420 control.40 ©UCB, DAP’ 97 Drawback of this Single Cycle Processor °Long cycle time: Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew °Cycle time for load is much longer than needed for all other instructions
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ceg3420 control.41 ©UCB, DAP’ 97 °Single cycle datapath => CPI=1, CCT => long °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary Control Datapath Memory Processor Input Output
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ceg3420 control.42 ©UCB, DAP’ 97 Where to get more information? °Chapter 5.1 to 5.3 of your text book: David Patterson and John Hennessy, “Computer Organization & Design: The Hardware / Software Interface,” Second Edition, Morgan Kaufman Publishers, San Mateo, California, 1998. °One of the best PhD thesis on processor design: Manolis Katevenis, “Reduced Instruction Set Computer Architecture for VLSI,” PhD Dissertation, EECS, U C Berkeley, 1982. °For a reference on the MIPS architecture: Gerry Kane, “MIPS RISC Architecture,” Prentice Hall.
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