1. CS 140 Lecture 17 System Designs III Professor CK Cheng CSE Dept. UC San Diego 1

2. System Designs 1.Methodology 2.Hierarchy 3.Flow and Process 4.Technology-Oriented Construction 2

3. Digital Designs vs Computer Architectures Instruction Set (H.Chapter 6, CSE141) –Bottleneck: Silicon Area, Power Data Path (H.Chapter 7.1-7.3) Control Subsystem (H.Chapter 7.1-7.3) Memory Management (Chapter 8, CSE141) –Bottleneck: IO, Memory Latency 3

4. Design Process Program of Hardware Description List of Data Operations Data Path –Read control signals. Output conditions Control Subsystem –Read conditions. Output control signals 4

5. Example: Multiplication Arithmetic Z=X x Y M<=0 For i=n-1 to 0 –If Y i =1, M<=M+X 2 i Z<=M 5 Input X, Y Output Z Variable M, i M<=0 For i=n-1 to 0 –If Y n-1 =1, M<=M+X –Shift Y left by one bit –If i != 0, shift M left by one bit Z<=M

6. Implementation: Example { Input X, Y type bit-vector, start type boolean; Local-Object A, B,M, i type bit-vector; Output Z type bit-vector, done type boolean; S0: If start’ goto S0; S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0; S2: If B 15 = 0 goto S4 || i<=i+1; S3: M <= M+A; S4: if i>= 16, goto S6 S5: M<=Shift(M,L,1) || B<=Shift(B,L,1) || goto S2; S6: Z<= M || done<= 1|| goto S0; } 6

7. Implementation: Example { Input X, Y type bit-vector, start type boolean; Local-Object A, B,M, i type bit-vector; Output Z type bit-vector, done type boolean; S0: If start’ goto S0; S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0; S2: If B 15 = 0 goto S4 || i<=i+1; S3: M <= M+A; S4: if i>= 16, goto S6 S5: M<=Shift(M,L,1) || B<=Shift(B,L,1) || goto S2; S6: Z<= M || done<= 1|| goto S0; } 7

8. Z=XY Data Subsystem Control Subsystem C 0-7 B 15 i 4 X Y start Z done 16 32 8

9. A <= X B <=Y M<=0 i<=0 i<=i+ 1 M<=M+A M<=Shift(M,L,1) B<=Shift(B,L,1) Z<=M operation A  Load (X) B  Load (Y) M  Clear(M) i  Clear(i) i  INC(i) M  Add(M,A) M  SHL(M) B  SHL(B) Wires control C 0 C 2 C 4 C 6 C 7 C 5 C 1 C 3 9 Data Path Subsystem

10. 10 Control Unit B C 0-7 start done i Data Path Subsystem A C0C0 C1C1 Add M C4C4 C5C5 X Z LD CLR LD i C6C6 C7C7 CLR Inc B C2C2 C3C3 Y LD SHL B i 16 SHL

11. Control Subsystem 11 C0C1C2C3C4C5C6C7done S0000000001 S1101010100 S2000000010 S3000001000 S4000000000 S5010100000 S6000000001 A C0C0 C1C1 Add M C4C4 C5C5 X Z LD CLR LD i C6C6 C7C7 CLR Inc B C2C2 C3C3 Y LD SHL B i 16 SHL

12. Control Subsystem 12 S0 S1 S2 S3 S5 S4 B start’ start i B ’ i ’ S6

13. 13 Exercises: 1.Implement the control subsystem with one-hot state machine design. 2.Try to reduce the latency of the whole system.