1. 1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 4/12/2006 Top Level Layout Design Manager: Abhishek Jajoo

2. 2Status  Project chosen: 16 bit Delta-Sigma ADC - Basic specs defined  Architecture  Schematic  Floor Planning  Revised Layout Dimensions  Layout Progress  Top Level Analog  Delta/Sigma Modulator  Low Pass Filter – DRC, LVS, Simulated  Top Level Digital  PII – DRC, LVS, Simulated  Sinc Filter – DRC, LVS, Simulated  Clock Divider – DRC, LVS, Simulated  Simulation / Verification  All Digital Modules Verified  All Analog Modules Verified  Overall/Top Verified  Optimized Layout  Analog Components  PII Function  Sinc Filter

3. 3 Design Decisions Trade area from capacitor to resistor Trade area from capacitor to resistor Widening VDD and GND lines for sinc and pii function Widening VDD and GND lines for sinc and pii function

4. 4 Analog Progress Delta/Sigma Modulator Delta/Sigma Modulator Completed DRC/LVS of Module Completed DRC/LVS of Module Completed Schematic/Layout Verification Completed Schematic/Layout Verification Working on Analog Top Level Layout Working on Analog Top Level Layout Working on Optimizing Module Layout Working on Optimizing Module Layout

5. 5 Modulator -schematic

6. 6 Schematic Simulation

7. 7 Extracted Simulation

8. 8Extracted Schematic

9. 9 Effects of Mismatch on ΔΣ Matched RC and Diff Pair Transistors Increased 10% Diff Pair Size Decreased 10% Diff Pair Size Only 10% RC Mismatch

10. 10 Analog Mismatch

11. 11 Digital Progress Working on widening the lines Working on widening the lines >> mostly complete in the sinc filter and pii function Making the bitslices of the sinc filter tighter Making the bitslices of the sinc filter tighter

12. 12 PII Zoom - Layout

13. 13 PII Function - new Layout

14. 14 Preliminary Top Level - Layout

15. 15 Layout Power/Timing Module Power AreaT-Count SchematicExtracted Clock Divider6.534mW@20KHz 7.138mW@20KHz 1,740um^2334 2nd Order Sinc Filter14.2mW@5.12MHz & 20KHz 15.33mW@5.12MHz & 20KHz 17,967um^23296 PII Function260.7nW@20KHz292.0nW@20KHz17,955um^22782 Decimator (Top Digital)20.99mW22.76mW45,474um^26412 Analog Op-Amps/Modulator ~162uW (Op Amp Power) --20 Low Pass FilterMax ~ 327.6uW 59,899um^20 Modulator (Top Analog)Max ~ 837.4uW ~137,764um^26,432

16. 16 Problems and Questions Extracted comparator can't seem to handle the load of the extracted D flip flop Extracted comparator can't seem to handle the load of the extracted D flip flop The best way to debug extracted views? The best way to debug extracted views?