1. Middle presentation Dynamic System on Programmable Chip By: Nir Shahar and Amir Kleinhendler Supervisor: Ina Rivkin Spring/Winter 2006

2. Global Project goals Designing A New Experiment for undergraduate students at the High Speed Digital Systems Laboratory Based on a Dynamic System (using SOPC platform). Dynamic Peripheral Designing and Implementation.

3. Implementing a Simple Dynamic Peripheral. Learning The FPGA Methodology. – FPGA Logical Structure. – XUP Board, Virtex II pro, PPC. – FPGA Design Flow. – FPGA Design Tools ( EDK, ISE, Chip-Scope). –Implementing a Simple Dynamic Peripheral. Learning VHDL Design Methodology. –VHDL for Synthesis. –MODEL-SIM for Simulation. –HDL Design Tool. First Semester Goals

4. The Dynamic System Concept When we simulate a problem we can dynamically remove or replace a peripheral in-order to fix the simulated problem. Option 1 Option 2 Option 3

5. Status Update Completed our learning of all the design tools (VHDL,EDK,HDL Designer, Chip Scope). Completed our learning of XUP board, design flow. Building a small system that includes one simple original peripheral. Building a small system that includes one peripheral with regular HW register and full address approach.

6. Simple Peripheral Block Diagram IP to Bus Buffers User select logic Read Write controller Bus to IP register This implementation is used for one simple bus register access

7. Simple peripheral with full address approach Block Diagram Register addresses controller IP to Bus Buffers User select logic Read Write controller Bus to IP register

8. First Semester System In this semester we shall implement a few simple peripherals to demonstrate the principal of a dynamic system.

9. First Semester System Functionality Block Diagram Illustrate timing problems Illustrate logic problems Illustrate software problems Illustrate Sequence problems

10. REQUIRED FUNCTION – Adder : A xor B xor C REQUIRED FUNCTION – Adder : A xor B xor C ABCF 0011 0101 0110 1001 1010 1100 1111

11. FIRST OPTION : (A and B) xor C ‘0’‘1’ ‘0’‘1’ ‘0’‘1’ ‘0’ ‘1’

12. SECOND OPTION : (A or B) xor C ‘0’‘1’ ‘0’‘1’ ‘0’‘1’ ‘0’ ‘1’

13. THIRD OPTION : (A xor B) xor C ‘0’‘1’ ‘0’‘1’ ‘0’‘1’ ‘0’‘1’ ‘0’

14. Time Line Block diagram Learning Tools and Basic of FPGA Design Designing a small SOPC Learning and Designing Dynamic SOPC Designing the Experiment Concept Creating the Experiment Design Files Writing an Experiment Folio

15. First semester Time Line 26-31.3.06 – Learning FPGA + SOPC Basic 6-13.4.06 – Learning VIRTEX II Pro 14-21.4.06 – Learning XUP Board 14-21.4.06 – Learning Design Flow 26.3-30.4.06 – Learning EDK 22-30.4.06 – Learning PPC 1-15.5.06 - Learning VHDL & Learning MODELSIM 15.5-15.6.06- Designing a System with a simple peripheral 15.6-15.8.06- Designing a Dynamic System on the FPGA. –15.6-1.7.06- First two logic blocks implementation (counter & adder ) –1.7-15.7.06- another two logic blocks implementation (stop light & flash light ) –15.7-15.8.06- integration & debug of the complete design. First semester concluding presentation.

16. QUESTIONS

17. Designing The New Dynamic System Experiment. Building The Experiment Files ( EDK ). Simulating The Completed Experiment. Building an Experiment Folio. –Pre-experiment learning kit ( includes preparation questions ). –Preparing an experiment booklet. –Preparing a station startup script. Second Semester Goals