1. UC Berkeley B. Nikolić Architecture choices MAC Unit Addr Gen  P Prog Mem Embedded Processor (lpArm) Direct Mapped Hardware Embedded FPGA DSP (e.g. TI 320CXX ) Flexibility Area or Power Reconfigurable Processors (Maia) Factor of 100-1000 100-1000 MOPS/mW 10-100 MOPS/mW.5-5 MIPS/mW Brodersen & Rabaey

2. UC Berkeley B. Nikolić Low power digital implementation flexibility vs. energy efficiency Example: Correlator for wideband CDMA Radio: Microprocessor Arm 6 core (5V, 20 MHz): 2765 nJ167697 fJsec Programmable Logic Xilinx 4003 (5V, 64 MHz) 394 nJ394 fJsec Dedicated ASIC Datapath (1.5V, 64 MHz) 1.2 nJ1.04 fJsec * Energy/symbol * Normalized Energy-Delay Product (5V)

3. UC Berkeley B. Nikolić Architectural strategy for energy reduction l Initial voltage, V init, and clock rate, f clk l Energy required for one sample of computation, over time,Tsamp, is given by sampclkinit TfCVE 2 

4. UC Berkeley B. Nikolić Parallel units allows energy reduction with constant throughput l N parallel units allow an N-fold clock rate reduction l Supply voltage can be reduced to V final l Final energy is 2 2 )(                init final initsamp clk final V V ET N f NCV

5. UC Berkeley B. Nikolić The Overhead of Von Neumann DSP processor with 1 multiplier (25 mm 2 ) 16x16 multiplier (.05 mm 2 ) Why time multiplex to save area if the overhead is much greater than the area saved? This problem is getting worse as technology scales