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Behaviour and Performance of Interactive Multi-player Game Servers Ahmed Abdelkhalek, Angelos Bilas, and Andreas Moshovos
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Introduction Investigate the scalability of services provided by servers Multi-player games are enabled by a central server FPS typically supports under 70 users
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The First Experiment 32 PII-400 MHz computers Machines connected on the same LAN Quake (FPS game) 1 human controlled player with the rest being automated players
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Server incoming network throughput per client
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Server outgoing network throughput per client
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Server response size
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Server received request rate
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Server response rate (relies/s)
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Server execution time breakdown
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Graphics Rendering Time for Clients
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Server response rate as measured at the clients
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The Second Experiment Each client computer simulates 16 players Compare statistics on two maps, a small map and a big one use PIII-800 MHz computer as server later Use EMON to monitor the CPU statistics
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Server response rate (small map)
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Server outgoing network throughout per client
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Server execution time breakdown (small map)
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Request processing time at the server (small map)
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Server response size (small map)
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Server response rate (large map)
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Server execution time breakdown (large map)
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Request processing time at the server (large map)
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Server response rate (800MHz processors, large map)
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Request processing time at the server (800MHz processors, large map)
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Server execution time breakdown (800MHz processors, large map)
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Server CPU Behaviour
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Conclusion Network bandwidth is not an issue Incoming bandwidth per player on server is constant with increasing number of players Outgoing bandwidth per player increases with increasing number of players Memory requirement is not an issue Use server response rate and average response time for evaluation
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Conclusion (cont’d) Can support between 60 to 100 players with the equipment Server utilization increases linearly with the number of players Doubling the speed of CPU results in a less than double increase in the number of players Room for improving server performance at the microprocessor architecture level
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