1. Lens Aberration Aware Timing-Driven Placement Andrew B. Kahng †‡* Chul-Hong Park ‡ Puneet Sharma ‡ Qinke Wang † CSE † and ECE ‡ Departments, UC San Diego *Blaze DFM, Inc., Sunnyvale, CA

2. 2 Outline Lens Aberration and Background Placement Formulation and Solver Aberration-Aware Timing Flow Experiments Summary

3. 3 Lithography System Lithography tool images a complex chip pattern with billions of pixels on wafer Full-wafer exposure  Step-and-repeat  Step-and-scan system Produce multiple copies of chips with one mask Illumination Source Condenser Lens Projection Lens Lens Slit Mask Wafer Lens

4. 4 Lens Aberration Lens Aberrations: image distortion induced by imperfect lens system Optical path differences among light rays  wavefront deviation from reference sphere at the exit pupil  blur and distortion of images Variety of effects on lithographic imaging  shifts in image position, image asymmetry, reduction of process window Image plane Illumination ray

5. 5 Zernike Aberration Coefficients Zernike Coefficients represent wavefront aberrations 36 Zernike terms Coma  image asymmetry, pattern-dependent image shift Astigmatism  CD difference between horizontal, vertical lines Spherical  changes best DOF between dense/isolated patterns ComaAstigmatism Spherical

6. 6 Zernike Coefficients with lens field Slit scans from one side of the field to another Zernike coefficients vary with position in the lens field  CD also varies along horizontal direction  CD stays constant along vertical direction Astigmatism variation  pushes designer toward single-directional layouts Gate CDs of each master cell change according to lens position Device performances vary across the chips in a lens field Astigmatism X-coma Y-coma Spherical Lens Position different Reticle (mask) map same

7. 7 An Example: Coma Aberration Coma Aberration  path difference in the horizontal direction  CD asymmetry between left and right devices in pattern shown CD variation: -15nm to 20nm in early 193nm scanners  CD skews between devices increase circuit delay

8. 8 Impact on Gate CD Impact on average cell delay varies with location in lens field  Average CD 93nm – 97nm for NAND2X4 Different devices in a cell affected differently CD skew: Max difference in CD of devices in a cell  CD Skew up to 5nm for NAND2X4

9. 9 Impact on Gate Delay Impact on average cell delay varies with location in lens field  NAND2X4 delay varies between -2% and 2% Delay skew: Max difference over all timing arc delays  NAND2X4 has delay skew increase of up to 60% Input capacitance and slews increase with CD  Predictable “fast” and “slow” regions due to aberration  Place setup-critical cells in the fast regions, and place hold-critical cells in the slow regions

10. 10 Outline Lens Aberration and Background Placement Formulation and Solver Aberration-Aware Timing Flow Experiments Summary

11. 11 Placer: APlace Global Placement (NP-hard) as a Constrained Nonlinear Optimization Problem: We divide the placement area into uniform bins, and seek to minimize total half-perimeter wirelength (HPWL) under the constraint that total cell area in every bin is equalized. min HPWL (x,y) s.t. D g (x,y) = D for each global bin g D g (x,y) : density function that corresponds to the total cell area in a given global bin “g” D : average cell area over all global bins

12. 12 Non-Linear Optimization Apply smooth approximation of placement objectives: wirelength, density function, etc. Quadratic Penalty method Solve sequence of unconstrained minimization problems for sequence of µ  0 Conjugate Gradient solver Find unconstrained minimum of a high-dimensional function Memory required is only linear in problem size  adaptable to large-scale placement problems

13. 13 High Quality and Extensibility IBM ISPD'05 Placement Contest Testcases directly derived from industrial ASIC designs, preserve physical structure of design Large amounts of whitespace, fixed blocks and (peripheral or area) I/Os, up to 2.1 million components APlace2.0 was contest winner Strong Extensibility Wirelength-Driven Mixed-Size Placement [ISPD04, ICCAD04, TCAD05, ISPD05, ICCAD05] Timing Driven Placement [ICCAD04] Power Aware Placement [DAC05] Voltage Drop Aware Placement [ICCD05] Aberration-Aware Placement [DATE06]

14. 14 Aberr-Aware Placement Formulation Goal: Minimize total timing-weighted delays of timing- critical cells and total timing-weighted net wirelength WWL is sum of timing-weighted net HPWL values W a is weight of the aberration-aware timing-driven objective g tv (x v ) is delay function for cell v’s model t v If there are multiple (n>1) chips, g i t v (x v ) is delay function for i th chip We consider the maximum delay of cell v over all copies  improve performance of slowest chips (with pessimism)

15. 15 Weight Function  : timing-criticality exponent µ: expected improvement of the longest (or shortest) delay T s = (1-µ)max π {delay(π)} for setup-critical path T h = (1+µ)min π {delay(π)} for hold-critical path slack s (π) = T s -delay(π): slack of a setup-critical path π slack h (π) = delay(π)-T h : slack of a hold-critical path π where Assign timing weights to cells based on timing criticality and path sharing  Cell on a timing critical path receives a heavy weight  Compute a weight for each timing-critical path  Obtain the timing weight of a cell by summing up the weights of timing critical paths

16. 16 Smoothing of Delay Variations Purpose of smoothing Delay functions have accurate values only at discrete locations Use linear interpolation to get cell delays at continuous positions in lens field  can compute gradients Smoothing factor β

17. 17 Outline Lens Aberration and Background Placement Formulation and Solver Aberration-Aware Timing Flow Experiments Summary

18. 18 Standard Timing Analysis Flow Standard Cell GDS SPICE Netlist Library Characterization SPICE Model Delay Extraction Problem: With aberration, two instances of the same master should have different timing models !

19. 19 Aberration-Aware Timing Flow Standard Cell GDS Print Image GDS Lens Position SRAF Generation OPC Lithography Simulation CD Measurement SPICE Netlist Library Characterization Transistor-level Timing Library (TTL) Delay LUTs LVS SPICE Model Two main steps Construct litho models  get simulated gate CDs of each instance Generate timing library models of all masters for different locations CD Measurement

20. 20 OPC GDSII Generation SRAF: Sub-Resolution Assist Feature (or Scattering Bar) Extremely narrow lines  do not print on wafer Enhance process window OPC: Optical Proximity Correction Layout modification to match photo-resist edges to layout edge  limited ability to compensate for aberration-induced CD error Standard Cell GDS SRAF Generation OPC CD Measurement SPICE Netlist Library Characterization Transistor-level Timing Library (TTL) Delay LUTs LVS SPICE Model Print Image GDS Lens Position Lithography Simulation Original GDSII with SRAF GDSII with OPC

21. 21 Lithography Simulation Print Image GDS Lens Position Lithography Simulation Standard Cell GDS SRAF Generation OPC Library Characterization Transistor-level Timing Library (TTL) Delay LUTs SPICE Model CD Measurement SPICE Netlist LVS Zernike coefficients 8 measured sampling position  19 coefficient sets with 1.5mm stepsize using linear interpolation Lithography simulation Post-OPC GDSII and aberration parameters  lithography simulation at 19 different field locations with different lithography models Use Calibre PrintImage to generate different contour images Model-1 Model-2Model-3Model-4Model-5Model-6 19 Different Field Positions  Measure CD of each MOS device at all positions in lens field

22. 22 Transistor-Level Timing Library CD Measurement SPICE Netlist Library Characterization Transistor-level Timing Library (TTL) Delay LUTs LVS SPICE Model Standard Cell GDS Print Image GDS Lens Position SRAF Generation OPC Lithography Simulation LVS mapping GDSII does not have device names, while SPICE identifies devices by their names Perform LVS to establish correspondence Transistor-level timing library Contain variants for each cell corresponding to different locations in the field Capture aberration-induced CD skew as delay skew A simplified look-up table is also created for analytical placement

23. 23 Aberration-Aware Placement Flow Timing-driven placement flow Send intermediate placement to TrialRoute  perform a fast global and detailed routing Change the type of each cell in the netlist with horizontal position of lens field Use a commercial tool  perform accurate aberration- aware STA with TTLs Use Conjugate Gradient Solver Total timing-weighted cell delays are minimized Netlist - Wire length - Timing (MCT) - Run Time Transistor-Level Timing Library Delay LUTs Aberration- Aware STA TrialRoute Aberration- Aware Placement

24. 24 Outline Lens Aberration and Background Placement Formulation and Solver Aberration-Aware Timing Flow Experiments Summary

25. 25 Experimental Setup Mentor’s Calibre OPCpro and SBar OPC and SRAF insertion Cadence SOC Encounter and SignalStorm Placement & Route Library characterization Synopsys Design Compiler and PrimeTime Synthesis and static timing analysis (STA) Benchmark Circuit Artisan TSMC 90nm Library, RTL designs from OpenCores.org Design Utilization (%) Chip Size (mm) #Cells#Nets AES600.501730417465 JPEG601.41118321125036

26. 26 Experimental Run Two Placement Runs AberrPl_WL ► Perform with HPWL objective and no RC extraction before timing analysis ► Compare with wirelength-driven APlace (APlace_WL) AberrPl_TD ► Perform with timing-driven wirelength objective and RC extraction before timing analysis ► Compare with timing-driven APlace (APlace_TD) Experimental Metrics HPWL, Wirelength and Minimum Cycle Time (MCT)

27. 27 Comparison of APlace with AberrPl AberrPL_WL: MCT(↑4.7%), HPWL(↓3.0%) and WL(↓1.4%) for AES MCT(↑8.4%), HPWL(↓2.7%) and WL(↓2.4%) for JPEG AberrPL_TD: MCT(↑9.8%), HPWL(↓1.5%) and WL(↓1.7%) for JPEG DesignMethodPlaceTrialRouteAberrSTA HPWL (e9)CPU (s)WL (e5)#viasMCT (nm) AESAPlace_WL1.0326316.1831.1281.67 AberrPl_WL1.0636166.2691.1741.59 Impr. (%)-3.012.34-1.39-4.124.66 APlace_TD1.0546726.2581.1293.85 AberrPl_TD1.0826546.4111.1273.53 Impr. (%)-2.682.75-2.440.188.38 JPEGAPlace_WL10.60436205.8917.5312.54 AberrPl_WL10.72738445.9667.5762.44 Impr. (%)-1.16-6.19-1.27-0.594.24 APlace_TD10.66537555.9157.55510.86 AberrPl_TD10.82239676.0137.6239.79 Impr. (%)-1.47-5.64-1.66-0.909.80

28. 28 Impact of Delay Ratio AberrPL_WLAberrPL_TD MCT, HPWL, and routed wirelength impacts with delay ratio Performed for circuit AES with a variety of delay ratios AberrPl_WL: MCT improvement increases with delay ratio to 4.7% AberrPl_TD: MCT reduction of 8.4% with 2.7% increase of HPWL and 2.4% increase of trial routed wirelength

29. 29 Impact of Scaling Effect of chip size on performance improvement Circuit AES using AberrPl_WL with a variety of scaling factors Performance improvement decreases with the number of copies ► As the chip is small, the variation is too small to have benefit ► Chip with large size will benefit more from AberrPl techniques

30. 30 Outline Lens Aberration and Background Placement Formulation and Solver Aberration-Aware Timing Flow Experiments Summary

31. 31 Summary We have proposed an accurate aberration-aware timing analysis flow and a novel aberration aware timing-driven placement technique Maximum improvement of AberrPlace Minimum clock cycle time: ~5% Wirelength increase: ~2% Ongoing research We plan to improve our approach so that the total value (i.e., “selling price”) of all chips is maximized Aberration-aware OPC (AberrOPC) can correct CD variation of each gate  will combine AberrPlace and AberrOPC to enhance CD accuracy, reduce delay impact

32. Thank You!