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Dec. 6, 2005ELEC6970-001 Class Presentation1 Reducing Switching Capacitance Using Buffers Brad Hill
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Dec. 6, 2005ELEC6970-001 Class Presentation2 Objective Reduce the Power of a Multiplier Circuit Do this with out Increasing the Delay of the Critical Path
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Dec. 6, 2005ELEC6970-001 Class Presentation3 Problem of Fanout Fanout Increases the Capacitive Load on the Driving Transistor RC time constant increases due to increased load capacitance Delay of the circuit increases
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Dec. 6, 2005ELEC6970-001 Class Presentation4 Reasoning Behind Buffers Single Fanout The transistor driving the buffer now sees a single fanout instead of a large fanout There is a steady increase in transistor size between stages Extra Large Drive Transistors Reduce Charging Resistance Increase Drive Capacity Lowers the RC time constant and speeds up the switching to reduce delay This does not directly reduce power but can be used to our advantage
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Dec. 6, 2005ELEC6970-001 Class Presentation5 2x Buffer
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Dec. 6, 2005ELEC6970-001 Class Presentation6 Multiplier Simulated cells and circuits with multiple cells compared results Found the best configuration of the buffers in the circuits to reduce the delay
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Dec. 6, 2005ELEC6970-001 Class Presentation7 Critical Path
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Dec. 6, 2005ELEC6970-001 Class Presentation8 Cell with Buffers The fanout of both Sum_in and Carry_in in the Cell is 6 These two signals benefit the most from buffers
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Dec. 6, 2005ELEC6970-001 Class Presentation9 Delay of a Cell without Buffers (1.8V)
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Dec. 6, 2005ELEC6970-001 Class Presentation10 Cell with Buffers (1.8V)
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Dec. 6, 2005ELEC6970-001 Class Presentation11 Cell Delay (1.75V)
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Dec. 6, 2005ELEC6970-001 Class Presentation12 Cell With Buffer Delay (1.75V)
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Dec. 6, 2005ELEC6970-001 Class Presentation13 Comparison Dynamic(W)Static(W)Delay(S) Supply Voltage Single Cell33.86u171.14p14.942p1.8V Cell with buffers 35.08u243.98p-129.56p1.8V No Buffers31.44u162.10p16.129p1.75V Buffers32.34u230.87p-120.778p1.75V Difference-1.52u59.73p-135.72-0.05V
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Dec. 6, 2005ELEC6970-001 Class Presentation14 Two Cells with Buffers The two cells represent two cells in the middle of the multiplier A, B, B1, Sum_in, Carry_in, and Sum_in1 are driven for the simulation
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Dec. 6, 2005ELEC6970-001 Class Presentation15 Cells 1.8V
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Dec. 6, 2005ELEC6970-001 Class Presentation16 Cells no Buffers 1.75V
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Dec. 6, 2005ELEC6970-001 Class Presentation17 Cells with Buffers 1.75V
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Dec. 6, 2005ELEC6970-001 Class Presentation18 Two Cell Simulation Comparison Dynamic( W) Static(W)Delay(S) Supply Voltage No Buffers 467.126u342.282p12.081p1.8V Buffers488.136u487.96p-7.85p1.8V No Buffers 418.677u 324.2060 p 13.510p1.75V Buffers438.90u461.75p5.095p1.75V Differenc e -28.226u119.552p-6.986p-0.05V
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Dec. 6, 2005ELEC6970-001 Class Presentation19 Area of Cell GateArea AO32288 XOR310 XNOR282 NAND88 Total968
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Dec. 6, 2005ELEC6970-001 Class Presentation20 Increase in Area Area of a 2x Buffer 84 Area of Buffered Cell 1136 Percent Increase 17.36%
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Dec. 6, 2005ELEC6970-001 Class Presentation21 Conclusions Strategically placed buffers can greatly decrease the delay of a circuit This reduction in delay can be used to offset the increase in delay due to some power reduction schemes
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