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A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning Hsiao-Pin Su 1 2 Allen C.-H. Wu 1 Youn-Long Lin 1 1 Department of.

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Presentation on theme: "A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning Hsiao-Pin Su 1 2 Allen C.-H. Wu 1 Youn-Long Lin 1 1 Department of."— Presentation transcript:

1 A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning Hsiao-Pin Su 1 2 Allen C.-H. Wu 1 Youn-Long Lin 1 1 Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C 2 Taiwan Semiconductor Manufacturing Co., Ltd. {Email: robin@nthucad.cs.nthu.edu.tw}

2 Outline Introduction Motivation The Proposed Method Experiments Conclusions

3 A Typical HDL-based Design Flow HDL Synthesis Floorplanning P & R Timing Analysis OK? RC-Extraction Delay Calculation Chip Layout Yes No HDL Synthesis Floorplanning P & R RC-Extraction Delay Calculation Timing Analysis Chip Layout No HDL Description Yes OK?

4 Motivation Develop a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvement.

5 Motivation (cont’) Top HM1 HM2 SM2SM3 SM4 SM1 HM1HM2 SM1SM3SM4SM2

6 HM1SM1 SM2 HM2 SM4 SM3 ( b ) Motivation (cont’) HM2 HM1SM1 SM2 The critical path delay SM4 SM3 Resynthesize SM3 by relaxing its timing constraints. SM3 Saved area ( a ) Slack > 0

7 HM1SM1 HM2 SM2 SM3 SM4 ( d ) Motivation(cont’) HM2 SM3 HM1SM1 ( c ) SM4 SM2 Resynthesize SM2 by tightening its timing constraints. SM2 Timing violation

8 Considerations How to decide HDL design hierarchy? How to guide soft-macro placement by utilizing hierarchy information? How to integrate design tasks and point tools at different design level to form a complete chip design methodology? How to exploit the interaction between different design tasks?

9 The Proposed Method HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Module Resynthesis Soft-Macro Placement Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

10 The Proposed Method HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location HDL Synthesis

11 The Proposed Method HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

12 Hierarchy-tree Construction The main objective is to preserve the design hierarchy information from HDL design description during soft macro formation. Top HM1 HM2 SM2SM3 SM4 SM1

13 Soft-Macro Formation Clock-based clustering  Group the macros connected to the same clock source into the same cluster. Decomposition of large soft-macros.  A large macro is too rigid for macro Placement. Clustering of small soft-macros.  Many small macros increase the computational complexity.

14 Clock-based Clustering Partition circuit based on the clock connection. Localize the distribution of clock signal.  If clock signal is distributed to many modules then it may have difficulty to balance the clock skew or cause area penalty when balance the clock skew on top module. HM1 HM2 SM4

15 Large-Macro Decomposition Split cluster if cluster size is larger than the size threshold by using FM partitioning method. Big size threshold:

16 Small-Macros Clustering Merge clusters if cluster size is smaller than the size threshold. Small size threshold:

17 Clustering Cost Function Cost Function:  Connectivity Consideration:  Criticality Consideration:

18 The Proposed Method HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

19 The Proposed Method HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

20 Block Placement HM IO

21 The Proposed Method HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

22 The Proposed Method HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

23 Soft-Macro Placement Inputs: a set of soft-macros and the available area for soft macros. Outputs: the locations of all soft macros. Algorithm:  1st step: force-directed-based placement.  2nd step: line-sweep-based soft-macro assignment.

24 Force-directed-based Placement HM IO

25 HM IO HM IO Force-directed-based Placement SM2SM3 SM4 SM1 HM IO HM IO

26 Soft-Macro Area Extraction HM SM area IO

27 Sweeping-based Soft-Macro Assignment ( Y direction ) SM1 SM2 SM3 SM4 X Y SM3 SM1 HM SM area SM2 & SM4

28 Sweeping-based Soft-Macro Assignment SM1 SM2 SM3 SM4 X Y SM3 SM1 SM area HM Sweeping-based Soft-Macro Assignment X direction SM4 SM2

29 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

30 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Soft-Macro Placement Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location

31 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement

32 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement

33 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis Timing Ok & no more area improvement P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement

34 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement

35 Module Resynthesis Slack Computation:  Calculate the slack value for each inter-macro signal path Soft-Macro Resynthesis Candidate Selection:  If there exists a negative slack value of any soft-macro then pick the one with highest negative slack as the candidate to resynthesize using tightened timing constraint  If all timing satisfies the timing constraint then pick the one with highest positive slack value as the candidate to resynthesize using relaxed timing constraint

36 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement

37 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement Soft-Macro Placement

38 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement P&R

39 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement RC Extraction & Delay Calculation

40 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement Post-layout Timing Analysis

41 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement Timing Ok & no more area improvement

42 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement Yes

43 The Proposed Flow HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis Module Resynthesis P&R Block Placement Soft-Macro Formation Yes No Soft-Macro Formation Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Soft-Macro Placement Timing Ok & no more area improvement Chip Layout

44 The Experiment Environment Setup HDL Description HDL Synthesis RC Extraction & Delay Calculation Chip Layout Post-layout Timing Analysis P&R Block Placement Yes No Yes RTL netlist Timing constraint Soft-Macro group Hard macro location Routed database SDF file Soft-Macro location Timing Ok & no more area improvement Soft-Macro Placement Soft-Macro Formation Module Resynthesis Synopsys Cadence (Block Placement) Avant!(P&R) Avant!(STAR-RC) Avant!(STAR-DC) Synopsys (Design Time)

45 Benchmarks

46 Results (Ind1 @ TSMC 0.5um)

47 Results (Ind2 @ TSMC 0.5um)

48 Results (Ind3 @ TSMC 0.5um)

49 Results (Ind2 @ 0.25um)

50 Results (Ind2 @ 0.5um) The original critical path and new critical path of Ind2 using the 0.5um library after two resynthesis iterations

51 Conclusions Preserving design hierarchy for soft-macro placement leads to significant improvements in circuit timing. Exploiting the interaction between HDL-synthesis, floorplanning, and place-and-route is important to design quality. Many open problems need to be studied, such as the initial timing budgeting for each module, place hard-macro and soft-macro simultaneously.

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