1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 27 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

4. Current Version Wire routing on each block

5. Refined Floorplan

6. Flow Control FSM

9. Enter / Leaving Counter

11. Shift Reg. 11 bits input, store in 10 registers.

12. The First bit of all reg. row Shifting Signal : to choose which arms we should store in Shifting Signal Clock

13. 2:1MUX 11 bit x 10 (from shift reg.) input, 11 bit x 10 output

14. Enable Signal Some input signals Output

15. 16:1 MUX 11 bit x 16 wire input, 11 bit output to ALU

16. Selection signals Output Different inputs

17. DEMUX Control CLK and all Selections signal as inputs of AND5, the output of AND5 to be a trigger signal for the next stage. (DFF-Register)

18. CLK Selection Signals Output

19. DEMUX + Reg.

20. CLK Selection Data Input Output of Reg

21. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

22. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

23. Layout  All basic logic layouts were been done, for instance, inverter, NAND, NOR, XOR, 1-bit register, 2:1 MUX, AND, OR, buffer, transmission gate, comparator and so on.

24. 2:1 MUXRegister

25. Mult/Add Update  Mirror Adder V2 completed  Compacted down  Height ~ 10x10  Why so big?  Given the Array multiplier, there are ten FAs lined up together with one input coming from the partial products. This allows a room for a wire bus over the FAs for the inputs via Metal 3  All other smaller modules completed  HA, and, XOR, inv  Buffer  Two stages of buffering will be added to the Array Multiplier instead of sizing up transistors.  Mult  Will be arranged such that it will look similar to the schematic with 10 FAs lined up next to each other over and over  The inputs will be generated from partial products coming in from the right side (Vertically arranged array of AND Gates)  The outputs will then run out to the left of the array Multiplier  This week  Array Mult & Partial Product Generation

26. Mirror Adder V1(Last Week)

27. Mirror Adder V2

28. Calibration To find out specific Cg’, beta ratio, and transition time for better estimation. Cg’ = 9.26fF/um Beta = 2.42 Tran. time = 88 ps (FO4) There might be a problem with beta ratio, need to confirm this later.

29. Schematic for Clock Not quite sure is that valid to build this block by this way, since there are VCVSs in it.

30. Waveform for Clock The period is about 1.275 ns (16FO4). Need dividers to generate slower clock.

31. Schematic for FSM Use non-ideal signals as inputs and put loads after each output.(7.5fF assume minimum size load on next stage.) Output loads Non-ideal inputs

32. Waveform for FSM(1) The are fewer glitches than previous. Transition time is kind of longer.

33. Waveform for FSM(2) Transition time is about 300ps for now. Since it still works fine, might not need to consider buffers later.

34. Schematic for Comparator The same structure for FSM and input signals for the chip.

35. Waveform for Comparator This is an example of comparing with 10. A signal is generated when both inputs are equal.

36. Layout for Logic Blocks Standard Cells The height for each block is 6.48um for fitting four lines and some extra spacing for possible modification. DRC and LVS clean. INVNAND2NAND3NOR2NOR3

37. Layout for Logic Blocks Standard Cells AOI1_2AOI2_2 XNOR

38. Layout for Logic Blocks Standard Cells XOR Half Adder 1-bit Comparator

39. FSM decoder Try to let global lines passing above transistors to save routing spacing.

40. FSM Next State Stuck over here for global routing. Need to find out another way to fit 19 lines in this block.

41. Issues  A little problem with these standard cells. They have the same height but forget to take substrate contacts into consideration.  Hard to share vdd or gnd in some cases.  Future work: fix this problem and finish preliminary layout for each block.

42. Question ?