1. 17.11.05 ONEBAT Meeting November 17, 2005 EPFL contribution Samuel Rey-Mermet, Paul Muralt

2. 17.11.05 Outline -New design for PEN -New photolithographic masks for PEN -Process flow -CGO dry etching -Lift-off -Ni plating -Patent -Main achievements -Milestones -Future work

3. 17.11.05 New designs for PEN PATENT PENDING Ni grid without current collector Ni grid with current collector

4. 17.11.05 New photolithographic masks 6 Masks: Current collector, electrolyte, seed layer, mould, anode and membrane. Grid and current collector line width: 5 um Hexagone side: 50 um Hexagone diagonal: 100 um Contact anode (4 x 6 mm 2 ) Contact cathode (6 x 4 mm 2 ) Membrane (diam.5 mm) 2.4 cm Connecting lines for eplating Ni grid Current collector

5. 17.11.05 Process Flow Current collector deposition Photo. Mask 1 CC etch Dry etch CC Deposition of electrolyte PATENT PENDING

6. 17.11.05 Process Flow Photo. Mask 2 Electrolyte etch Electrolyte dry etch Photo. Mask 3 Seed layer Deposition seed layer PATENT PENDING

7. 17.11.05 Process Flow Lift-off seed layer Photo. Mask 4 Mould eplating Grid eplating Resist removal PATENT PENDING

8. 17.11.05 Process Flow Depostion porous anode (anode etch ?) Photo. Mask 6 Si etch Si backside etch Depostion porous cathode PATENT PENDING

9. 17.11.05 Process Flow Summary 16 main steps: Wafer 1 is before step 13 Critical points: Lift-off definition Cr/Au must be replaced by Ni Cathode & Anode deposition (LC Ni-CGO ~Ok, NMW) Si dry etch (first test ok) Dicing (Laser?)

10. 17.11.05 CGO dry etching ECR Plasma RF chuck 2.45 GHz RF 13.56 MHz Water cooled Effect of the working pressure and rf power (chuck) on the etching rate of PZT thin film, selectivity for 60 W. V beam V acc Ar, CF4, CCl4

11. 17.11.05 CGO dry etching Etching rate for V beam /V acc =2, at 5 x 10 -4 mBar, with 16 sccm Ar, 2 sccm CCl 4, 4 sccm CF 4, 80 W RF bias power

12. 17.11.05 Evaporation 1 m Designed for lift-off 1.5 10 -6 mBar after 1h. Cr, Au, Ti, Al, Ni

13. 17.11.05 Lift-off Lift-off is improved Remaining parts of the seed-layer, broken grids… 100 um

14. 17.11.05 Ni eplating 100 um Pt CC 100 nm thick CGO 150- 200 nm thick Ni grid 5 um thick

15. 17.11.05 Patent A PCT patent application is being prepared and filed before December 16. Annoying: Patent on grid by semiconductor process (CVD) US 2005/0115889 (Liliput?) filed in 9/2003, 8 months after our invention. Lucky: No conductive grid, no electrolytic deposition claimed

16. 17.11.05 Main achievements 100  m 50  m Ni grids Ni grids with CGO

17. 17.11.05 Milestones WP 1.1 Electrolyte –Dense, crack free, CGO 80/20OK –Conductivity=0.5 S/m @500°COK –Microstructure charact.OK –Electrical charac. of membranenot OK –Stress measur.OK WP 1.2 Anode –Ni-CGO, 500 S/cm @ RT in air, ~OK porosity? –Thermal stabilitynot tested, grid ok –Stress measur.not tested, no problem WP 1.3 Cathode –LSCFtested by PLD, not OK –Stressnot tested, –Stress measur.not tested,

18. 17.11.05 Milestones WP 1.4 Microfab. and electrical testing –PEN with contactsin progress (anode, cathode from NMW) –1st PENin progress (step 12 of 16) –Concept Ni gridOK –Redesign PEN and contactMask OK, Process Flow in progress –Integration of Ni gridImprovement in progress

19. 17.11.05 Next Fabrication of a PEN including Ni-grid and NMW electrodes wafer 1: status:step #12/16 13=anode dep (NMW), 14/15=Si-etch, 16=cathode dep (NMW) wafers 2-3: with better seed layer lift off and better Ni-grid Thermal stability testing of this 1st PEN. Electrical testing of this 1st PEN.