1. 專題報告 指導教授 曾王道 961428 陳映蓉 961556 賴亭文

2. T HE COMPITITION 教育部主辦「九十八學年度大學校院積體電路電腦 輔助設計 (CAD) 軟體製作競賽」 題目：定題組 Ａ２組 題目內容： Multi-Core ATPG

3. ATPG acronym for both A utomatic T est P attern G eneration and A utomatic T est P attern G enerator electronic design automation method/technology To find faulty circuit behaviors.

4. P ARALLEL ATPG As the size and complexity of ICs continue to grow, ATPG time is getting longer. multi ‐ core processors to make Parallel ATPG

5. ATPG V.S. Parallel ATPG

6. G OAL develop an ATPG program fast run time few generated patterns high fault coverage under the given multi ‐ core computing environment.

7. F AULT COLLAPSING

9. E XAMPLE

11. T HE RESULTS OF THE EXAMPLE PI G0 PI G1 PI G2 PI G3 PI G5 PI G6 PI G7 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0

12. O UR I NPLEMENTATION We use fork() to create a new process to implement the multicore ATPG. fork() The fork () function shall create a new process. then we have a child process, and a parent process. The two process would run by the same time to implement the multicore ATPG.

13. 執行結果

14. T HE END