1. Combinational Logic Chapter 4

2. Digital Circuits 2 4.1 Introduction Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs.

3. Digital Circuits 3 4.2 Combinational Circuits Logic circuits for digital system Sequential circuits contain memory elements the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs

4. Digital Circuits 4 A combinational circuits 2 n possible combinations of input values Specific functions Adders, subtractors, comparators, decoders, encoders, and multiplexers MSI circuits or standard cells Combinational Logic Circuit n input variables m output variables

5. Digital Circuits 5 4-3 Analysis Procedure A combinational circuit make sure that it is combinational not sequential No feedback path derive its Boolean functions (truth table) design verification a verbal explanation of its function

6. Digital Circuits 6 A straight-forward procedure F 2 = AB+AC+BC T 1 = A+B+C T 2 = ABC T 3 = F2'T1 F 1 = T3+T2

7. Digital Circuits 7 F 1 = T 3 +T 2 = F 2 'T 1 +ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C')(B'+C')(A+B+C)+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B'C+AB'C'+ABC A full-adder F 1 : the sum F 2 : the carry

8. Digital Circuits 8 The truth table

9. Digital Circuits 9 4-4 Design Procedure The design procedure of combinational circuits State the problem (system spec.) determine the inputs and outputs the input and output variables are assigned symbols derive the truth table derive the simplified Boolean functions draw the logic diagram and verify the correctness

10. Digital Circuits 10 Functional description Boolean function HDL (Hardware description language) Verilog HDL VHDL Schematic entry Logic minimization number of gates number of inputs to a gate propagation delay number of interconnection limitations of the driving capabilities

11. Digital Circuits 11 Code conversion example BCD to excess-3 code The truth table

12. Digital Circuits 12 The maps

13. Digital Circuits 13 The simplified functions z = D' y = CD +C'D' x = B'C + B'D+BC'D' w = A+BC+BD Another implementation z = D' y = CD +C'D'= CD + (C+D)' x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+BC+BD

14. Digital Circuits 14 The logic diagram

15. Digital Circuits 15 4-5 Binary Adder-Subtractor Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10 two input variables: x, y two output variables: C (carry), S (sum) truth table

16. Digital Circuits 16 S = x'y+xy' C = xy the flexibility for implementation S=x  y S = (x+y)(x'+y') S' = xy+x'y' S = (C+x'y')' C = xy = (x'+y')'

17. Digital Circuits 17

18. Digital Circuits 18 Full-Adder The arithmetic sum of three input bits three input bits x, y: two significant bits z: the carry bit from the previous lower significant bit Two output bits: C, S

19. Digital Circuits 19

20. Digital Circuits 20 S = x'y'z+x'yz'+ xy'z'+xyz C = xy + xz + yz S = z  (x  y) = z'(xy'+x'y)+z(xy'+x'y)' = z'xy'+z'x'y+z((x'+y)(x+y')) = xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy

21. Digital Circuits 21 Binary adder

22. Digital Circuits 22 Carry propagation when the correct outputs are available the critical path counts (the worst case) (A 1,B 1,C 1 ) > C 2 > C 3 > C 4 > (C 5,S 4 ) > 8 gate levels

23. Digital Circuits 23 Reduce the carry propagation delay employ faster gates look-ahead carry (more complex mechanism, yet faster) carry propagate: P i = A i  B i carry generate: G i = A i B i sum: S i = P i  C i carry: C i+1 = G i +P i C i C 1 = G 0 +P 0 C 0 C 2 = G 1 +P 1 C 1 = G 1 +P 1 (G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0 C 3 = G 2 +P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 + P 2 P 1 P 0 C 0

24. Digital Circuits 24 Logic diagram

25. Digital Circuits 25 4-bit carry-look ahead adder propagation delay

26. Digital Circuits 26 Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor M=0, A+B; M=1, A+B’+1

27. Digital Circuits 27 Overflow The storage is limited Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V = 0, no overflow; V = 1, overflow Example:

28. Digital Circuits 28 4-6 Decimal Adder Add two BCD's 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches A truth table with 2^9 entries use binary full Adders the sum <= 9 + 9 + 1 = 19 binary to BCD

29. Digital Circuits 29 BCD Adder: The truth table

30. Digital Circuits 30 Modifications are needed if the sum > 9 C = 1 K = 1 Z 8 Z 4 = 1 Z 8 Z 2 = 1 modification:  (10) d or +6 C = K +Z 8 Z 4 + Z 8 Z 2

31. Digital Circuits 31 Block diagram

32. Digital Circuits 32 Binary Multiplier Partial products – AND operations Fig. 4.15 Two-bit by two-bit binary multiplier.

33. Digital Circuits 33 4-bit by 3-bit binary multiplier Fig. 4.16 Four-bit by three-bit binary multiplier.

34. Digital Circuits 34 4-8 Magnitude Comparator The comparison of two numbers outputs: A>B, A=B, A<B Design Approaches the truth table 2 2n entries - too cumbersome for large n use inherent regularity of the problem reduce design efforts reduce human errors

35. Digital Circuits 35 Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 1 =B 1 equality: x i = A i B i +A i 'B i ' (A=B) = x 3 x 2 x 1 x 0 (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A>B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Implementation x i = (A i B i '+A i 'B i )'

36. Digital Circuits 36 Fig. 4.17 Four-bit magnitude comparator.

37. Digital Circuits 37 4-9 Decoder A n-to-m decoder a binary code of n bits = 2 n distinct information n input variables; up to 2 n output lines only one output can be active (high) at any time

38. Digital Circuits 38 An implementation Fig. 4.18 Three-to-eight-line decoder.

39. Digital Circuits 39 Combinational logic implementation each output = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables

40. Digital Circuits 40 Demultiplexers a decoder with an enable input receive information on a single line and transmits it on one of 2 n possible output lines Fig. 4.19 Two-to-four-line decoder with enable input

41. Digital Circuits 41 Decoder/demultiplexers 第三版內容，參考用 !

42. Digital Circuits 42 Expansion two 3-to-8 decoder: a 4-to-16 deocder a 5-to-32 decoder? Fig. 4.20 4  16 decoder constructed with two 3  8 decoders

43. Digital Circuits 43 Combination Logic Implementation each output = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables A full-adder S(x,y,x)=  (1,2,4,7) C(x,y,z)=  (3,5,6,7) Fig. 4.21 Implementation of a full adder with a decoder

44. Digital Circuits 44 two possible approaches using decoder OR(minterms of F): k inputs NOR(minterms of F'): 2 n  k inputs In general, it is not a practical implementation

45. Digital Circuits 45 4-10 Encoders The inverse function of a decoder The encoder can be implemented with three OR gates.

46. Digital Circuits 46 An implementation limitations illegal input: e.g. D 3 =D 6 =1 the output = 111 (¹3 and ¹6) 第三版內容，參考用 !

47. Digital Circuits 47 Priority Encoder resolve the ambiguity of illegal inputs only one of the input is encoded D 3 has the highest priority D 0 has the lowest priority X: don't-care conditions V: valid output indicator

48. Digital Circuits 48 ■ The maps for simplifying outputs x and y Fig. 4.22 Maps for a priority encoder

49. Digital Circuits 49 ■ Implementation of priority Fig. 4.23 Four-input priority encoder

50. Digital Circuits 50 4-11 Multiplexers select binary information from one of many input lines and direct it to a single output line 2 n input lines, n selection lines and one output line e.g.: 2-to-1-line multiplexer Fig. 4.24 Two-to-one-line multiplexer

51. Digital Circuits 51 4-to-1-line multiplexer Fig. 4.25 Four-to-one-line multiplexer

52. Digital Circuits 52 Note n-to- 2 n decoder add the 2 n input lines to each AND gate OR(all AND gates) an enable input (an option)

53. Digital Circuits 53 Fig. 4.26 Quadruple two-to-one-line multiplexer

54. Digital Circuits 54 Boolean function implementation MUX: a decoder + an OR gate 2 n -to-1 MUX can implement any Boolean function of n input variable a better solution: implement any Boolean function of n+1 input variable n of these variables: the selection lines the remaining variable: the inputs

55. Digital Circuits 55 an example: F(A,B,C) =  (1,2,6,7) Fig. 4.27 Implementing a Boolean function with a multiplexer

56. Digital Circuits 56 Procedure: assign an ordering sequence of the input variable the rightmost variable (D) will be used for the input lines assign the remaining n-1 variables to the selection lines w.r.t. their corresponding sequence construct the truth table consider a pair of consecutive minterms starting from m 0 determine the input lines

57. Digital Circuits 57 Fig. 4.28 Implementing a four-input function with a multiplexer Example: F(A, B, C, D) =  (1, 3, 4, 11, 12, 13, 14, 15)

58. Digital Circuits 58 Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) Fig. 4.29 Graphic symbol for a three-state buffer

59. Digital Circuits 59 Example: Four-to-one-line multiplexer Fig. 4.30 Multiplexer with three-state gates

60. Digital Circuits 60 4-12 HDL Models of Combinational Circuits ▓ Modeling Styles:

61. Digital Circuits 61 Gate-level Modeling ▓ The four-valued logic truth tables for the and, or, xor, and not primitives

62. Digital Circuits 62 Gate-level Modeling Example: output [0: 3] D; wire [7: 0] SUM; 1. The first statement declares an output vector D with four bits, 0 through 3. 2. The second declares a wire vector SUM with eight bits numbered 7 through 0.

63. Digital Circuits 63 HDL Example 4-1 ■ Two-to-one-line decoder

64. Digital Circuits 64 HDL Example 4-2 ■ Four-bit adder: bottom-up hierarchical description

65. Digital Circuits 65 HDL Example 4-2 (continued)

66. Digital Circuits 66 Three-State Gates ■ Statement: gate name (output, input, control); Fig. 4.31 Three-state gates

67. Digital Circuits 67 Three-State Gates ■ Examples of gate instantiation

68. Digital Circuits 68 Fig. 4.32 Two-to-one-line multiplexer with three-state buffers

69. Digital Circuits 69 Dataflow Modeling ■ Verilog HDL operators Example: assign Y = (A & S) | (B & ~S)

70. Digital Circuits 70 HDL Example 4.3  Dataflow description of a 2-to-4-line decoder

71. Digital Circuits 71 HDL Example 4-4  Dataflow description of 4-bit adder

72. Digital Circuits 72 HDL Example 4-5  Dataflow description of 4-bit magnitude comparator

73. Digital Circuits 73 HDL Example 4-6  Dataflow description of a 2-to-1-line multiplexer  Conditional operator (?:) Condition ? True-expression : false-expression Example: continuous assignment assign OUT = select ? A : B

74. Digital Circuits 74 Behavioral Modeling  if statement: if (select) OUT = A;  Behavioral description of a 2-to-1-line multiplexer HDL Example 4-7

75. Digital Circuits 75 HDL Example 4-8  Behavioral description of a 4-to-1-line multiplexer

76. Digital Circuits 76 Writing a Simple Test Bench  initial block Three-bit truth table

77. Digital Circuits 77 Writing a Simple Test Bench  Interaction between stimulus and design modules

78. Digital Circuits 78 Writing a Simple Test Bench  Stimulus module  System tasks for display

79. Digital Circuits 79  Syntax for $dispaly, $write, and $monitor: Example:

80. Digital Circuits 80 HDL Example 4-9  Stimulus module

81. Digital Circuits 81 HDL Example 4-9 (Continued)

82. Digital Circuits 82 HDL Example 4-10  Gate-level description of a full adder

83. Digital Circuits 83 HDL Example 4-10 (Continued)