1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 11 - Timing and Metastability Fall 2006

2. ECE 491 Fall 2006Lecture 11 - Timing2 Where we are  Last Time:  Verilog Coding - Quick Recap  The Datapath/Controller Abstraction  Today:  Timing  Synchronizers & Metastability

3. ECE 491 Fall 2006Lecture 11 - Timing3 Review - Flip-Flop Timing Characteristics  Propagation Delay t CQ  Setup time t setup  Hold time t h D Q clk D t setup thth CLK Q t CQ

4. ECE 491 Fall 2006Lecture 11 - Timing4 Review - Clocks in Sequential Circuits  Controls sequential circuit operation  Register outputs change at beginning of cycle  Combinational logic determines “next state”  Storage elements store new state Adder Mux Combinational LogicRegister Output Register Input Clock

5. ECE 491 Fall 2006Lecture 11 - Timing5 What Limits Clock Frequency?  Propagation delay - t prop Logic (including register outputs) Interconnect  Register setup time - t setup Adder Mux Combinational Logic Register Output Register Input Clock t prop t setup t clock > t prop + t setup t clock = t prop + t setup + t slack

6. ECE 491 Fall 2006Lecture 11 - Timing6 Timing in FPGA Design - Constraints  The constraints file specifies timing using the TIMESPEC directive #TIMESPEC = FROM : : TO : : ;  In the “s3board.v” file - using predefined groups # Time specifications for 50MHz clock # #TIMESPEC TS01 = FROM : FFS : TO : FFS : 20 ns; #TIMESPEC TS02 = FROM : RAMS : TO : FFS : 20 ns; #TIMESPEC TS03 = FROM : FFS : TO : RAMS : 20 ns; #TIMESPEC TS04 = FROM : RAMS : TO : RAMS : 20 ns; #TIMESPEC TS05 = FROM : FFS : TO : PADS : 20 ns; #TIMESPEC TS06 = FROM : PADS : TO : FFS : 20 ns; #TIMESPEC TS07 = FROM : PADS : TO : RAMS : 20 ns; #TIMESPEC TS08 = FROM : RAMS : TO : PADS : 20 ns;

7. ECE 491 Fall 2006Lecture 11 - Timing7 Synchronizers  Key idea: make sure inputs don’t change at a “bad time” in sequential circuits in1 in2 in3 00 1001 in1’ in1 0110 clk in1 NS 11 transient

8. ECE 491 Fall 2006Lecture 11 - Timing8 Adding Synchronizers  Add a D Flip-Flop on each asynchronous input  Synchronize each input only once  Q: What happens when set up & hold time violated? DQ clk in2_a in2_s DQ in1_a in1_s

9. ECE 491 Fall 2006Lecture 11 - Timing9 Metastability: When bad things happen to good synchronizers Q: What happens when t su / t h constraints violated? A: It depends, but there are three scenarios 1.Circuit correctly records new D value 1.Circuit retains old D value for an extra cycle 3.Metastability - “stuck” between legal 0 and 1 until it “resolves” CLK D Q1 Q2 Q3 t su thth t clk-q Resolution Time t r

10. ECE 491 Fall 2006Lecture 11 - Timing10 What Metastability Looks Like Image Source: www.fpga-faq.com

11. ECE 491 Fall 2006Lecture 11 - Timing11 Metastability  Two stable states  V o1 =L, V o2 =H  V o1 =H, V o2 =L  One metastable state  V o1 = V o2  Ugly characteristic: unbounded recovery time t r Graphic source: J. Rabaey, Digital Integrated Circuits, © Prentice-Hall, 1996 Metastable point

12. ECE 491 Fall 2006Lecture 11 - Timing12 Metastability - “Ball on the Hill” Analogy  Sides of hill = stable states  Top of hill = metastable state  Any small “push” (e.g., noise) will move the ball off the hill and into a stable state

13. ECE 491 Fall 2006Lecture 11 - Timing13 Metastability - Bad News / Good News  Bad news  Metastability is unavoidable  Recovery time is theoretically unbounded  Good news  Can empirically measure recovery times  Can use statistics from recovery times to make failure probability arbitrarily small  Most FPGAs are highly resistant to metastability

14. ECE 491 Fall 2006Lecture 11 - Timing14 Measuring Metastability Characteristics  Intentionally cause metastability many times  Measure recovery for each occurrence  Fit recovery times to exponential function t clk-q Number Of Occurrences Recovery Time

15. ECE 491 Fall 2006Lecture 11 - Timing15 Designing with Metastability  A synchronizer design at a given clock period provides a fixed amount of resolution time tr  Definition: a synchronization failure occurs when actual recovery time t r-actual > t r  For a given flip-flop, the mean time between failure (MTBF) is given by the formula f clk - System clock freq. a - asynchronous input rate of change.  - empirically derived constant T o - empirically derived constant t r - time available for resolution

16. ECE 491 Fall 2006Lecture 11 - Timing16 Determining Resolution Time t r  Must leave time for system to respond properly after resolution t r = t clk - t setup - t prop Comb. Logic D Q D Q clk t prop t su

17. ECE 491 Fall 2006Lecture 11 - Timing17 Resolution Time Example  Suppose that  fclk = 100MHz (t clk = 10ns)  a = 1MHz  t prop = 6.7ns  t setup = 1ns  Calculate t r :  t r = t clk - t setup - t prop  t r = 10ns - 6.7ns -1ns = 2.3ns Comb. Logic D Q D Q clk t prop =6.7ns t su =1ns

18. ECE 491 Fall 2006Lecture 11 - Timing18 MTBF Calculation Example  “Typical” values for a 0.25µm ASIC library flip-flop   = 0.31ns  T o = 9.6as “a” = 10 -18  t r = 2.3ns  MTBF = 20.1 days - unacceptable!

19. ECE 491 Fall 2006Lecture 11 - Timing19 What happens if we halve f clk ?  Suppose that  f clk = 50MHz (t clk = 20ns)  a = 1MHz  t prop = 6.7ns  t setup = 1ns  Calculate t r and MTBF:  t r = t clk - t setup - t prop  t r = 20ns - 6.7ns -1ns = 12.3ns  MTBF = 5.7 X 10 28 seconds = 1.8 X 10 21 years

20. ECE 491 Fall 2006Lecture 11 - Timing20 Reality Check: What about FPGAs?  Metastability info in FPGAs is scarce  One refrerence: Peter Alfke, “Metastability Delay and Mean Time Between Failures in Virtex-II Pro FFs”, October 2002.  Some statistical measurements for Virtex-II Pro FPGAs  Major conclusion: Metastability issues are not much of a problem

21. ECE 491 Fall 2006Lecture 11 - Timing21 MTBF Calculation Example - Virtex II Pro  Values from a Xilinx Technical note:   = 0.02ns - 0.05ps (assume 0.05ps)  T o = not given, but assume = 9.6as “a” = 10 -18  t r = 2.3ns  MTBF = 9.89 X 10 22 seconds = 7,53 X 10 16 years - not to worry!

22. ECE 491 Fall 2006Lecture 11 - Timing22 Alternative: Dual-Stage Synchronizer  Increased value for t r : t r = t clk - t su - t pr t r = 10ns - 1ns = 9ns Comb. Logic D Q D Q clk t prop t su D Q

23. ECE 491 Fall 2006Lecture 11 - Timing23 Dual-Stage MTBF Calculation  “Typical” values for a 0.25µm ASIC library flip-flop   = 0.31ns  T o = 9.6as “a” = 10 -18  t r = 9ns  MTBF = ?

24. ECE 491 Fall 2006Lecture 11 - Timing24 Other Synchronizer Alternatives  Metastability-hardened SYNC flip-flops  Multiple-Stage Synchronizers  Reduced-Clock Synchronizers

25. ECE 491 Fall 2006Lecture 11 - Timing25 What to Do About Metastability  Start with simple synchronizer (single flip-flop)  Calculate MTBF for your system  Decide if it's acceptable  If not, use a different design  OR different design:  Two-stage flip-flop  Reduced-clock synchronizers

26. ECE 491 Fall 2006Lecture 11 - Timing26 Coming Up  System Design  ASM Diagrams  Manchester Coding  Ethernet