1. Opportunities and Challenges for Better Than Worst­Case Design Todd Austin (presenter) Valeria Bertacco David Blaauw Trevor Mudge University of Michigan razor@eecs.umich.edu

2. Design-Time Verification and Optimization Traditional Worst-Case Design LH Time-to-Market LH Performance

3. Run-Time Verification Typical Case Optimization Better Than Worst-Case Design LH Time-to-Market LH Performance LH LH Time-to-Market Online Checker Hardware

4. Addressing Challenges in the Nanometer Regime  Design complexity  Billions and billions of transistors lead to untenable designs…  Soft errors upsets in logic and memory  Cosmic rays, alpha particles, neutrons, etc…  Uncertainty in design parameters  Process and temperature variation, supply noise…  Power/performance demands  Bounding performance, area, and battery life

5. Example BTWC Design: DIVA Checker  All core function is validated by checker  Simple checker detects and corrects faulty results, restarts core  Checker relaxes burden of correctness on core processor  Tolerates design errors, electrical faults, defects, and failures  Core has burden of accurate prediction, as checker is 15x slower  Core does heavy lifting, removes hazards that slow checker speculative instructions in-order with PC, inst, inputs, addr IFIDRENREG EX/ MEM SCHEDULER CHKCT PerformanceCorrectness CoreChecker Online Checker Hardware

6. Another BTWC Design: Razor Logic Main FF Shadow LatchMain FF clk clk_del 5 4 9 MEM 39 9  Double-sampling metastability tolerant latches detect timing errors  Second sample is correct-by-design  Microarchitectural support restores state  Timing errors treated like branch mispredictions Online Checker Hardware

7. recover IF Razor FF ID Razor FF EX Razor FF MEM (read-only) WB (reg/mem) errorbubble recover Razor FFStabilizer FFPC recover flushID bubble errorbubble flushID errorbubble flushID Flush Control flushID error Cycle:0 inst1inst2inst3inst4inst5 123456 inst6 Distributed Pipeline Recovery inst2inst7inst8 789 inst3inst4  Builds on existing branch prediction framework  Multiple cycle penalty for timing failure  Scalable design as all communication is local

8. Opportunities for CAD  Key observation: Infrequent faults in the core design are tolerable.  Opportunities:  Focus only on the critical components, no need to verify ad infinitum  Optimize performance/power for the most common scenarios (typical-case optimization)

9. Razor Opportunity: Typical-Case Energy Reduction E ref Voltage Control Function ...... Pipeline reset V dd E diff = E ref - E sample - E sample Voltage Regulator E diff error signals  Energy reduction can be realized with a simple proportional control function  Control algorithm implemented in software

10. Energy/Performance Characteristics Decreasing Supply Voltage Energy Energy of Processor Operations, E proc Energy of Pipeline Recovery, E recovery Total Energy, E total = E proc + E recovery Optimal E total Pipeline Throughput IPC Energy of Processor w/o Razor Support 50% 1%

11. Razor Opportunity: Typical-Case Optimized Adder Kogge-Stone Adder G0P0G0P0 G1P1G1P1 G2P2G2P2 G3P3G3P3 G4P4G4P4 G5P5G5P5 G6P6G6P6 G7P7G7P7 G8P8G8P8 G9P9G9P9 G 10 P 10 G 11 P 11 G 12 P 12 G 13 P 13 G 14 P 14 G 15 P 15 C in …

12. Carry Propagations for Random Data Bit Position Carry Distance Probability

13. Carry Propagations for Typical Data Carry Distance Bit Position Probability

14. Typical Case Optimized Adder G0P0G0P0 G1P1G1P1 G2P2G2P2 G3P3G3P3 G4P4G4P4 G5P5G5P5 G6P6G6P6 G7P7G7P7 G8P8G8P8 G9P9G9P9 G 10 P 10 G 11 P 11 G 12 P 12 G 13 P 13 G 14 P 14 G 15 P 15 C in … ripple carry circuit carry-lookahead circuit

15. Benefits of Typical Case Optimization Adder Topology Latency (in gate delays) Worst-CaseTypical-CaseRandom Kogge-Stone85.087.09 TCO Adder1283.033.69  Typical-case performance much better than worst case  Especially for typical-case optimized design

16. Core CAD Requirement: Observability of Circuit-Level Characteristics App Arch Config Architectural Simulator Architectural Simulator Circuit Simulator Circuit Simulator Output Arch Metrics Module Circuit Models Tech Models Circuit Metrics Inputs, Voltage, Constraints Delay, Power, Switching IFIDEXMEMWB Speed and Scope Fidelity and Observability  Circuit-Aware Architectural Simulator efficiently melds circuit simulation with architectural simulation

17. Additional CAD Opportunities  For synthesis:  Typical-case library characterization (e.g., pdf of delay)  Synthesize design for target performance, power, etc…  TCO-style optimizations possible for macro-modules  For verification:  Full formal verification for checker components  Profile-directed simulation-based verification for core  For testing:  Checker component can facilitate software-based manufacturing test of core components

18. Conclusions  Better than worst-case design abandons traditional worst-case design constraints  Couples complex designs with checkers  Enables CAD opportunities for typical-case optimization  Requires tool support for observability, synthesis and verification For more information: http://www.eecs.umich.edu/razor First tutorial at DATE, Munich, March 2005

19. Example BTWC Design: Razor Logic  Goal: reduce voltage margins with in-situ circuit timing error detection and correction  Approach:  Tune processor voltage based on error rate  Eliminate margins, run below critical voltage  Trade-off: power savings vs. overhead of correction  Technique is targeted toward embedded CPUs Traditional DVS Zero margin Sub-critical

20. Kogge-Stone Adder