1. Chapter 12 Three System Examples The Architecture of Computer Hardware and Systems Software: An Information Technology Approach 3rd Edition, Irv Englander John Wiley and Sons  2003 Wilson Wong, Bentley College Linda Senne, Bentley College

2. Chapter 12 Three System Examples 12-2 Three System Examples  X86 Family  PowerPC  IBM System 360/370/390/zSeries Family

3. Chapter 12 Three System Examples 12-3 The X86 Family  System Overview  The CPU  Registers  Instruction Set  Addressing Modes  Advanced Design Features  CPU Organization  The IA-64 Itanium Architecture

4. Chapter 12 Three System Examples 12-4 System Overview  Bus-oriented system I/O  Nonmaskable interrupts  Emergency situations  Single maskable interrupt  Supports 32 prioritized interrupts  IRQ0 to IRQ31  Upon receiving an interrupt, the CPU reads an address on the data lines that is used to jump to the interrupt routine

5. Chapter 12 Three System Examples 12-5 The CPU  Downward software compatibility  Disabled protected mode  Compatible with the original 8088 architecture  Original Intel 8088 CPU  16-bit processing and registers  16-bit internal data bus  8-bit external data bus  20-bit memory addressing – 1Mbyte total  Current Pentium CPUs  256-bit internal data bus  64-bit external data bus  2 levels of memory caching  Added floating point, multimedia, virtual storage, and multitasking support

6. Chapter 12 Three System Examples 12-6 Registers  8088, 8086, 80286  8 general-purpose registers  4 segment registers  1 flag register  Instruction pointer, and various control registers  80386 – added 2 segment registers  80486  8 80-bit floating point registers  Various floating point control registers  Pentium MMX  added registers for multimedia support  Pentium III  8 128-bit SIMD registers and control register

7. Chapter 12 Three System Examples 12-7 General Purpose Registers

8. Chapter 12 Three System Examples 12-8 Instruction Set and Format  Data transfer  Integer arithmetic  Branch  Bit manipulation, rotate and shift  String manipulation  Input / Output  Flag  Instructions added in later processors  Floating point  MMX  SIMD

9. Chapter 12 Three System Examples 12-9

10. Chapter 12 Three System Examples 12-10 Addressing Modes  Register  Immediate  Direct Addressing  Register Deferred Addressing  Base Addressing  Indexed Addressing  Base Indexed Addressing

11. Chapter 12 Three System Examples 12-11 Real Mode vs. Protected Mode Real Mode Protected Mode

12. Chapter 12 Three System Examples 12-12 Advanced Design Features  Protected Mode  Virtual storage support  Memory management  Multitasking support through efficient task switching  Virtual 8086 Mode  Can only be used when protected mode is activated  Calculates addresses the same way as real mode  Allows the system to run several 8086 tasks at once

13. Chapter 12 Three System Examples 12-13 X86 Protection Levels

14. Chapter 12 Three System Examples 12-14 CPU Organization  Early processors  Pipelined instruction fetch unit  Single integer execution unit  Current processors  Modern superscalar, pipelined design  Instruction decoder creates an intermediate set of micro-operations, μops  μops translate variable length and complex instructions into a 3-operand fixed length format

15. Chapter 12 Three System Examples 12-15 IA-64 Itanium Architecture  EPIC Architecture  Incorporates entire X86 instruction set and memory model  128 65-bit registers for programs  128 80-bit floating point registers  8 64-bit branch registers  64 1-bit predicate registers  Instead of instruction reordering, speculation and predication is used for branch predictions  IA-64 Mode  64-bit logical addresses  63-bit physical addresses

16. Chapter 12 Three System Examples 12-16 The PowerPC  System Overview  The CPU  Registers  Instruction Set  Addressing Modes  Advanced Design Features  CPU Organization

17. Chapter 12 Three System Examples 12-17 System Overview  Developed by Apple, Motorola, and IBM  Bus-oriented I/O architecture that can be interfaced with standard buses of other personal computers  Permits system components, bus adapters, and devices developed for other computers to be used with the PowerPC processor  Prioritized multi-level internal interrupts

18. Chapter 12 Three System Examples 12-18 The CPU  RISC design  32-bit implementation  32-bit registers and addressing  Up to 36-bit physical and 52-bit virtual addresses  64-bit implementation  64-bit registers and addressing  Superscalar design  Only 40 bits of interface to physical storage  Can run programs written for the 32-bit implementation  Supports floating point calculations, memory caching, and virtual memory  More current implementations also support vector processing

19. Chapter 12 Three System Examples 12-19 PowerPC Processor Characteristics

20. Chapter 12 Three System Examples 12-20 Registers  32 general purpose registers  32 floating point registers  Link register  Count register  Condition register  Fixed and floating point status registers  7400 processor series  32 128-bit vector processing registers  2 vector control registers

21. Chapter 12 Three System Examples 12-21 PowerPC User Registers

22. Chapter 12 Three System Examples 12-22 Instruction Set  Integer  Floating point  Load / Store  Flow Control  Processor Control  Memory Control  15 Different instruction formats  No specifically designed I/O instructions because PowerPC uses memory mapped I/O

23. Chapter 12 Three System Examples 12-23 Typical Instruction Formats

24. Chapter 12 Three System Examples 12-24 Addressing Modes

25. Chapter 12 Three System Examples 12-25 Address Translation Mechanisms

26. Chapter 12 Three System Examples 12-26 Advanced Design Features  Two levels of system access  Supervisor (privileged) state  User (problem) state  Memory is protected at the segment, page, and block levels  “Hint” bits in branching instructions aid in making accurate branch predictions

27. Chapter 12 Three System Examples 12-27 CPU Organization  Superscalar, pipelined design  Cache memory is standard  Execution units in the PowerPC 4751 CPU

28. Chapter 12 Three System Examples 12-28 The IBM 360/370/390/zSeries  Architectural Evolution of 360/370/390/zSeries Computers  The CPU  S/390 Registers  Instruction Set  Addressing Modes  Advanced Features  CPU Organization  S/390 Block Diagram

29. Chapter 12 Three System Examples 12-29 Architectural Evolution of 360/370/390/ zSeries Computers

30. Chapter 12 Three System Examples 12-30 The CPU  Architecture is compatible for every model of the zSeries  24-bit, 31-bit, and 64-bit addressing  16 address space registers permits access to one of fifteen 16EByte spaces  Present and previous Program Status Word (PSW) formats are supported  64-bit partitioned, segmented, and paged virtual storage and cache memory

31. Chapter 12 Three System Examples 12-31 zSeries Specifications

32. Chapter 12 Three System Examples 12-32 S/390 Registers  16 64-bit general purpose registers  16 64-bit floating point registers  16 special 64-bit control registers  16 access registers  Time-of-day clock register  Timer register  Clock comparator register  Prefix register  128-bit Program Status Word (PSW)

33. Chapter 12 Three System Examples 12-33 zSeries User Registers

34. Chapter 12 Three System Examples 12-34 Instruction Set  All zSystem instructions are 16 bits, 32 bits, or 64 bits in length  General instructions  Data transfer  Integer arithmetic and logical operations  Branches  Shifts  Decimal Instructions  Floating point instructions  Control instructions

35. Chapter 12 Three System Examples 12-35 Addressing Modes  Immediate  Register  Storage  Also known as base offset addressing  Storage Indexed  Similar to storage addressing with the addition of an index value

36. Chapter 12 Three System Examples 12-36 Address Translation Mechanisms

37. Chapter 12 Three System Examples 12-37 Real-to-Absolute Translation

38. Chapter 12 Three System Examples 12-38 Advanced Features  Many features can be enabled or disabled with simple control register instructions  Clock synchronization between systems  Cluster support with data integrity control and workload balancing  Built-in diagnostics that can shift work from one CPU to another  Multiple forms of hardware system protection  System Protection Features  Supervisory state  Problem state  Storage access protection is provided at the address space, segment, and page levels  Integrated cryptographic facility  Firewall protection

39. Chapter 12 Three System Examples 12-39 CPU Organization  S/360 and S/370  Traditional control unit – arithmetic/logic unit model  More current processors  Modern CPU design with multiple fetch and execution units

40. Chapter 12 Three System Examples 12-40 S/390 System Block Diagram

41. Chapter 12 Three System Examples 12-41 Copyright 2003 John Wiley & Sons All rights reserved. Reproduction or translation of this work beyond that permitted in Section 117 of the 1976 United States Copyright Act without express permission of the copyright owner is unlawful. Request for further information should be addressed to the permissions Department, John Wiley & Songs, Inc. The purchaser may make back-up copies for his/her own use only and not for distribution or resale. The Publisher assumes no responsibility for errors, omissions, or damages caused by the use of these programs or from the use of the information contained herein.”