1. EECS 150 - Components and Design Techniques for Digital Systems Lec 19 – Fixed Point Arithmetic & Register Transfers Level (RTL) Design 11/2/2004 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150 vote day

2. Introduction to High Level Digital Design High-level Design Specifies: –How data is moved around and operated on. –The architecture (sometimes called micro-architecture): »The organization of state elements and combinational logic blocks »Functional specification of combinational logic blocks Optimization –Deals with the task of modifying an architecture and data movement procedure to meet some particular design requirement: »performance, cost, power, or some combination. Most designers spend most of their time on high-level organization and optimization –modern CAD tools help fill in the low-level details and optimization »gate-level minimization, state-assignment, etc. –A great deal of the leverage on effecting performance, cost, and power comes at the high-level.

3. Recall: Computer Number Systems Positional notation –D n-1 D n-2 …D 0 represents D n-1 B n-1 + D n-2 B n-2 + …+ D 0 B 0 where D i  { 0, …, B-1 } 2s Complement –D n-1 D n-2 …D 0 represents: - D n-1 2 n-1 + D n-2 2 n-2 + …+ D 0 2 0 –MSB has negative weight Binary Point is effectively at the far right of the word 0000 0001 0010 0011 1000 0101 0110 0100 1001 1010 1011 1100 1101 0111 1110 1111 +0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 0000…

4. Representing Fractional Numbers Fixed-Point Positional notation –D n-k-1 D n-k-2 …D 0… D -k represents D n-k-1 B n-k-1 + D n-2 B n-2 + …+ D -k B -k where D i  { 0, …, B-1 } 2s Complement –D n-k-1 D n-2 …D -k represents: - D n-k-1 2 n-k-1 + D n-2 2 n-2 + …+ D -k 2 -k 0000 0001 0010 0011 1000 0101 0110 0100 1001 1010 1011 1100 1101 0111 1110 1111 +0 +1/4 +1/2 +3/4 +1 +5/4 +3/2 +7/4 -2 -7/4 -3/2 -5/4 -3/4 -1/2 -1/4

5. Circuits for Fixed-Point Arithmetic Adders? –identical circuit –Position of the binary point is entirely in the intepretation –Be sure the interpretations match »i.e. binary points line up Subtractors? Multipliers? –Position of the binary point just as you learned by hand –Mult Two n-bit numbers yields 2n-bit result with binary point determined by binary point of the inputs –2 -k * 2 -m = 2 -k-m + *

6. Example: Pong Project Pixel Position –Board 720 x 507 –10 bits each –BinPt to the far right Paddle –Pixel position –Velocity in pixels/frame »8 bits –PdlPos( f+1 ) = PdlPos( f ) + Vel every frame Ball –subpixel = pixel/256 –subframetime = frametime/256 »Note: pix per frame == subpix per subframe –Ball position represented as subpixels –Update subpixel position every subframe –Render pixel pos every frame –Max movement per frame »255/256 of a pixel 507 720

7. Arithmetic Representation Position of binary point represents a trade-off of range vs precision –Many digital designs operate in fixed point »Very efficient, but need to know the behavior of the intended algorithms »True for many software algorithms too –General purpose numerical computing generally done in floating point »Essentially scientific notation »Fixed sized field to represent the fractional part and fixed number of bits to represent the exponent »± 1.fraction x 2^ exp –Some DSP algorithms used block floating point »Fixed point, but for each block of numbers an additional value specifies the exponent.

8. system data-path control state registers combinational logic multiplexer comparator code registers registerlogic switching networks Design hierarchy

9. Levels of Design Representation Transfer Function Transistor Physics Devices Gates Circuits FlipFlops EE 40 HDL Machine Organization Instruction Set Arch Pgm Language Asm / Machine Lang CS 61C

10. A Standard High-level Organization Controller –accepts external and control input, generates control and external output and sequences the movement of data in the datapath. Datapath –is responsible for data manipulation. Usually includes a limited amount of storage. Memory –optional block used for long term storage of data structures. Standard model for CPUs, micro-controllers, many other digital sub-systems. Usually not nested. Often cascaded:

11. Announcements Homework due Friday as usual Mid Term on 11/9 “Putting it together” lecture on Thurs (by Stan) Review session –Monday November 8th from 5:30-8pm. Digital Design in the News –Prof. David Wagner, Digital Democracy vote day

12. Computer Organization Computer design as an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine –Inputs = machine instruction, datapath conditions –Outputs = register transfer control signals, ALU operation codes –Instruction interpretation = instruction fetch, decode, execute Datapath = functional units + registers + interconnect –Functional units = ALU, multipliers, dividers, etc. –Registers = program counter, shifters, storage registers –Interconenct = busses and wires Instruction Interpreter vs Fixed Function Device

13. Register Transfer Level Descriptions A standard high-level representation for describing systems. It follows from the fact that all synchronous digital system can be described as a set of state elements connected by combination logic (CL) blocks: RTL comprises a set of register transfers with optional operators as part of the transfer. Example: regA  regB regC  regA + regB if (start==1) regA  regC Personal style: –use “;” to separate transfers that occur on separate cycles. –Use “,” to separate transfers that occur on the same cycle. Example (2 cycles): regA  regB, regB  0; regC  regA;

14. RTL building blocks: Tri-State Buffers 0, 1, Z (high impedance state) in out OE if OE then Out = In else “disconnected” + out + OE in Basic Inverter Inverting Buffer (logical) + in OE out in OE Circuit Structure

15. Tri-States vs. Mux Sel 2:1 Mux 0 1 A B A Sel 0 B Sel 1 DECDEC Sel 0101 Scales poorly for high fan-in or wide bit widths Compact control Only point-to-point wires Buffer circuits simple! Scales nicely for high fan-in and wide bit widths! Often need to inputs come from physically separated parts of the design bus ties the datapath together

16. A Register Transfer Ld C A Sel 0 B Sel 1 DECDEC Sel 0101 C  A Sel  0; Ld  1 C  B Sel  1; Ld  1 Clk Sel Ld Clk A on Bus Ld C from Bus Bus B on Bus ? One of potentially many source regs goes on the bus to one or more destination regs Register transfer on the clock

17. Register Transfers - interconnect Point-to-point connection –Dedicated wires –Muxes on inputs of each register Common input from multiplexer –Load enables for each register –Control signals for multiplexer Common bus with output enables –Output enables and load enables for each register rt MUX rs MUX rd MUX R4 MUX rs MUX rtrdR4 BUS rsrtrdR4

18. Register Transfer – multiple busses One transfer per bus Each set of wires can carry one value State Elements –Registers –Register files –Memory Combinational Elements –Busses –ALUs –Memory (read) MUX rsrtrdR4

19. LD asserted during a lo-to-hi clock transition loads new data into FFs OE asserted causes FF state to be connected to output pins; otherwise they are left unconnected (high impedance) OE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD D7 D6 D5 D4 D3 D2 D1 D0 CLK Registers Selectively loaded – EN or LD input Output enable – OE input Multiple registers – group 4 or 8 in parallel

20. RE RB RA WE WB WA D3 D2 D1 D0 Q3 Q2 Q1 Q0 Register Files Collections of registers in one package –Two-dimensional array of FFs –Address used as index to a particular word –Separate read and write addresses so can do both at same time Ex: 4 by 4 register file –16 D-FFs –Organized as four words of four bits each –Write-enable (load) –Read-enable (output enable)

21. RD WR A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO3 IO2 IO1 IO0 Memories Larger Collections of Storage Elements –Implemented not as FFs but as much more efficient latches –High-density memories use 1-5 switches (transitors) per bit Ex: Static RAM – 1024 words each 4 bits wide –Once written, memory holds forever (not true for denser dynamic RAM) –Address lines to select word (10 lines for 1024 words) –Read enable »Same as output enable »Often called chip select »Permits connection of many chips into larger array –Write enable (same as load enable) –Bi-directional data lines »output when reading, input when writing

22. 16 AB SZN Operation 16 ALU Block Diagram –Input: data and operation to perform »Add, Sub, AND, OR, NOT, XOR, … –Output: result of operation and status information

23. Cin Ain Bin Sum Cout FA HA Ain Bin Sum Cin Cout HA Data Path (Hierarchy) Arithmetic circuits constructed in hierarchical and iterative fashion –each bit in datapath is functionally identical –4-bit, 8-bit, 16-bit, 32-bit datapaths

24. 16 Z N OP 16 ACREG 16 Example Data Path (ALU + Registers) Accumulator –Special register –One of the inputs to ALU –Output of ALU stored back in accumulator One-input Operation –Other operand and destination is accumulator register –AC <– AC op REG –”Single address instructions” »AC <– AC op Mem[addr]

25. 2 bits wide 1 bit wide Data Path (Bit-slice) Bit-slice concept: iterate to build n-bit wide datapaths Data bit busses run through the slice CO CIALU AC R0 from memory rs rt rd CO ALU AC R0 from memory rs rt rd CIALU AC R0 from memory rs rt rd

26. Example of Using RTL ACC  ACC + R0, R1  R0; ACC  ACC + R1, R0  R1; R0  ACC;  RTL description is used to sequence the operations on the datapath (dp). It becomes the high-level specification for the controller. Design of the FSM controller follows directly from the RTL sequence. FSM controls movement of data by controlling the multiplexor/tri-state control signals.

27. Example of Using RTL RTL often used as a starting point for designing both the dp and the control: example: regA  IN; regB  IN; regC  regA + regB; regB  regC; From this we can deduce: –IN must fanout to both regA and regB –regA and regB must output to an adder –the adder must output to regC –regB must take its input from a mux that selects between IN and regC What does the datapath look like: The controller:

28. List Processor Example RTL gives us a framework for making high-level optimizations. –Fixed function unit –Approach extends to instruction interpreters General design procedure outline: 1. Problem, Constraints, and Component Library Spec. 2. “Algorithm” Selection 3. Micro-architecture Specification 4. Analysis of Cost, Performance, Power 5. Optimizations, Variations 6. Detailed Design

29. 1. Problem Specification Design a circuit that forms the sum of all the 2's complements integers stored in a linked-list structure starting at memory address 0: All integers and pointers are 8-bit. The link-list is stored in a memory block with an 8-bit address port and 8-bit data port, as shown below. The pointer from the last element in the list is 0. At least one node in list. I/Os: –START resets to head of list and starts addition process. –DONE signals completion –R, Bus that holds the final result

30. 1. Other Specifications Design Constraints: –Usually the design specification puts a restriction on cost, performance, power or all. We will leave this unspecified for now and return to it later. Component Library: componentdelay simple logic gates0.5ns n-bit registerclk-to-Q=0.5ns setup=0.5ns (data and LD) n-bit 2-1 multiplexor1ns n-bit adder(2 log(n) + 2)ns memory10ns read (asynchronous read) zero compare0.5 log(n) (single ported memory) Are these reasonable?

31. 2. Algorithm Specification In this case the memory only allows one access per cycle, so the algorithm is limited to sequential execution. If in another case more input data is available at once, then a more parallel solution may be possible. Assume datapath state registers NEXT and SUM. –NEXT holds a pointer to the node in memory. –SUM holds the result of adding the node values to this point. If (START==1) NEXT  0, SUM  0; repeat { SUM  SUM + Memory[NEXT+1]; NEXT  Memory[NEXT]; } until (NEXT==0); R  SUM, DONE  1;

32. A_SEL 01 NEXT 0 1 + Memory D A ==0 + 01 SUM NEXT_SEL LD_NEXT NEXT_ZERO SUM_SEL LD_SUM 0 1 0 3. Architecture #1 Direct implementation of RTL description: Datapath Controller If (START==1) NEXT  0, SUM  0; repeat { SUM  SUM + Memory[NEXT+1]; NEXT  Memory[NEXT]; } until (NEXT==0); R  SUM, DONE  1;

33. 4. Analysis of Cost, Performance, and Power Skip Power for now. Cost: –How do we measure it? # of transistors? # of gates? # of CLBs? –Depends on implementation technology. Usually we are interested in comparing the relative cost of two competing implementations. (Save this for later) Performance: –2 clock cycles per number added. –What is the minimum clock period? –The controller might be on the critical path. Therefore we need to know the implementation, and controller input and output delay.

34. Possible Controller Implementation Based on this, what is the controller input and output delay?

35. 4. Analysis of Performance

36. Critical paths A_SEL 01 NEXT 0 1 + Memory D A ==0 + 01 SUM NEXT_SEL LD_NEXT NEXT_ZERO SUM_SEL LD_SUM 0 1 0

37. 4. Analysis of Performance Detailed timing: clock period (T) = max (clock period for each state) T > 31ns, F < 32 MHz Observation: COMPUTE_SUM state does most of the work. Most of the components are inactive in GET_NEXT state. GET_NEXT does: Memory access + … COMPUTE_SUM does: 8-bit add, memory access, 15-bit add + … Conclusion: Move one of the adds to GET_NEXT.

38. 5. Optimization Add new register named NUMA, for address of number to add. Update RTL to reflect our change (note still 2 cycles per iteration): If (START==1) NEXT  0, SUM  0, NUMA  1; repeat { SUM  SUM + Memory[NUMA]; NUMA  Memory[NEXT] + 1, NEXT  Memory[NEXT] ; } until (NEXT==0); R  SUM, DONE  1;

39. 5. Optimization Architecture #2: Incremental cost: addition of another register and mux. If (START==1) NEXT  0, SUM  0, NUMA  1; repeat { SUM  SUM + Memory[NUMA]; NUMA  Memory[NEXT] + 1, NEXT  Memory[NEXT] ; } until (NEXT==0); R  SUM, DONE  1;

40. 5. Optimization, Architecture #2 New timing: Clock Period (T) = max (clock period for each state) T > 23ns, F < 43Mhz Is this worth the extra cost? Can we lower the cost? Notice that the circuit now only performs one add on every cycle. Why not share the adder for both cycles?

41. 5. Optimization, Architecture #3 Incremental cost: –Addition of another mux and control. Removal of an 8-bit adder. Performance: –mux adds 1ns to cycle time. 24ns, 41.67MHz. Is the cost savings worth the performance degradation?