1.  Based on the resource constraints a lower bound on the iteration interval is estimated  Synthesis targeting reconfigurable logic (e.g. FPGA) faces the challenge of creating designs that comply with the resource & storage capacity of target device  Synthesis tools optimize latency and/or throughput  Often push the utilization of the device to its capacity  May lead to infeasible designs  With increasing popularity of portable devices demand for streaming multimedia applications are growing  Computationally intensive  Functional pipelining is shown to be effective  Early estimates of resource requirements very useful for faster design closure and design space exploration Thermal-aware and Low Power Optimizations for VLSI Synthesis Min Ni (m-ni@northwestern.edu) PhD Advisor : Prof. Seda Ogrenci Memik Department of EECS, Northwestern University Introduction Embedded ComputingMobile DevicesNetworking Planning Clock Period during Register Binding Leakage Power Aware Clock Skew Scheduling Problem Formulation Thermal-induced Leakage Power Optimization  Probabilistic push-and-pull method proposed to estimate data queuing cost for streaming accelerators  Estimates are within -14.4% and 12.4%  Given an unscheduled streaming DFG, G = (V, E) and a set of Resource Constraints  Find: The total number of registers needed at the output of all Functional Units Iteration Interval Estimation  Based on the ASAP and ALAP schedules minimum queue size of each node is estimated Determine Min. Queue Sizes of Edges  Based on the likelihood estimation of the facts that  Source may produce data before ALAP time  Sink may consume data after ASAP time  Probabilistic Push-and-Pull approach  Source node estimated to be pulled up by Δi  Sink node estimated to be pushed down by Δj  Expected values of Δi and Δj are calculated based upon  Contention for resources  More critical nodes than current node  Estimated Iteration Interval Refinement of Queue Sizes of Edges  Multiple nodes of sDFG mapped to a single FU enable sharing of the output queues  With fewer resources more nodes are mapped to FUs and queue sizes decrease  With more contention for resources outputs of operations have to be stored longer before it gets consumed Queue Estimates of FUs using Resource Constraint Correction Factor Application RC Set 1RC Set 2 dctCol8510315247.6364422.2 dctRow9511116851.4414919.5 hpf_med_cc157404347-14.1769119.7 lpf_gc_rgb221697508-27.110311713.6 lpr67150110-26.7586715.5 open307147-33.84434-22.7 Quant1013 0.013 0.0 RsvpLPR67150110-26.7586715.5 Average92.7212.4181.9-14.453.660.312.4  Estimation technique evaluated on a set of industrial multimedia applications  Applications include video and image compression and filtering algorithms, as well as applications such as license plate recognition  Different resource constraints chosen for each application  Develop integrated framework to estimate hardware cost for streaming accelerators implemented on reconfigurable fabric from unscheduled data flow graphs Self-heating Aware Optimal Wire Sizing