1. Sep. 26, 2001Agrawal: Stratified Sampling1 Stratified Sampling for Fault Coverage of VLSI Systems Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974 va@agere.com http://cm.bell-labs.com/cm/cs/who/va September 26, 2001 Collaborators: Pradip Thaker, Acorn Networks, and Mona Zaghloul, GWU

2. Sep. 26, 2001Agrawal: Stratified Sampling2 VLSI System Design Register-transfer level (RTL) design and verification Logic synthesis Test generation Design and test data for manufacturing 90-100% stuck-at fault coverage required Timing and physical design

3. Sep. 26, 2001Agrawal: Stratified Sampling3 Problem n Accurately estimate the gate-level fault coverage for a VLSI system at the RT-level n Advantages: Improve test Improve design Avoid expensive design changes n Previous approaches do not accurately represent gate-level fault coverage (function errors, mutation, statement faults, branch faults, etc.)

4. Sep. 26, 2001Agrawal: Stratified Sampling4 Solution n Model faults as representative sample of the targeted (gate-level stuck-at) faults. n Treat the coverage in an RTL module as a statistical sampling estimate. n For a multi-module VLSI system, combine module coverages according to the stratified sampling technique.

5. Sep. 26, 2001Agrawal: Stratified Sampling5 Outline of Talk n Introduction to fault sampling. n RTL fault model and application to modules. n Coverage in a multi-module system: Need for stratified sampling Stratum weights Experimental results n Conclusion n References

6. Sep. 26, 2001Agrawal: Stratified Sampling6 Fault Sampling n A randomly selected subset (sample) of faults is simulated. n Measured coverage in the sample is used to estimate fault coverage in the entire circuit. n Advantage: Saving in computing resources (CPU time and memory.) n Disadvantage: Limited data on undetected faults.

7. Sep. 26, 2001Agrawal: Stratified Sampling7 Random Sampling Model All faults with a fixed but unknown coverage Detected fault Undetected fault Random picking N p = total number of faults (population size) C = fault coverage (unknown) N s = sample size N s << N p c = sample coverage (a random variable)

8. Sep. 26, 2001Agrawal: Stratified Sampling8 Probability Density of Sample Coverage, c (x--C ) 2 -- ------------ 1 2  2 p (x ) = Prob(x < c < x +dx ) = -------------- e  2  1/2 p (x ) C C +3  C -3  1.0 x Sample coverage C (1 - C) Variance  2 = ------------ N s Mean = C Sampling error   x

9. Sep. 26, 2001Agrawal: Stratified Sampling9 Sampling Error Bounds C (1 - C ) | x - C | = 3  --------------  1/2 N s Solving the quadratic equation for C, we get the 3-sigma (99.8% confidence) estimate (Agrawal-Kato, 1990): 4.5 C 3  = x ------- [1 + 0.44 N s x (1 - x )] 1/2 N s Where N s is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults.   Millot, 1923

10. Sep. 26, 2001Agrawal: Stratified Sampling10 An RTL Fault Model (ITC-2000) n Language operators are assumed to be fault- free n Variables (map onto signal lines) contain faults stuck-at-0 stuck-at-1 n Only one fault is applied at a time (single fault assumption)

11. Sep. 26, 2001Agrawal: Stratified Sampling11 RTL Fault Injection n Not affected by faults: Synthetic operators + - * >= <= == != Boolean operators & | ^ ~ Logical operators && || ! Sequential elements (flip-flops & latches) n Faults introduced in signal variables (stems and fan-outs) n Separate faults for bits of data words

12. Sep. 26, 2001Agrawal: Stratified Sampling12 Fault Modeling for Boolean Operators

13. Sep. 26, 2001Agrawal: Stratified Sampling13 Stem and Fan-out Fault Modeling n RTL fan-out faults: if(X) then Z=Y; else Z=!Y; n Unique RTL fault is placed on each fan-out of each bit of a variable n Unique RTL fault on each stem

14. Sep. 26, 2001Agrawal: Stratified Sampling14 More RTL Faults

15. Sep. 26, 2001Agrawal: Stratified Sampling15 Observations and Assumption: RTL Faults n RTL faults may have detection probability distribution similar to that of collapsed gate-level faults n Statistically, an RTL fault-list approximates a random sample from the gate-level fault-list n Number of RTL faults vs. gate-level faults depends on Level of RTL description Synthesis procedure used to convert RTL to gate level

16. Sep. 26, 2001Agrawal: Stratified Sampling16 RTL Fault Simulation n Analogous to gate-level approach n Faults injected in RTL code of the design description by a C++ parser; a simulatable logic buffer element inserted at fault site n Fault report contains statistics on detected and undetected RTL faults n Cadence’s Verifault-XL used as RTL fault simulator

17. Sep. 26, 2001Agrawal: Stratified Sampling17 Estimation Error for Module Fault Coverage n RTL fault coverage assumed to be an estimate of the collapsed gate-fault coverage within statistical bound [Agrawal and Kato, D&T, 1990] : a = 3.00 for confidence probability of 99.8% c = ratio of detected to total number of RTL faults M = number of gate faults N = number of RTL faults, k = 1 - N/M

18. Sep. 26, 2001Agrawal: Stratified Sampling18 DSP Interface Module (3,168 Gates)

19. Sep. 26, 2001Agrawal: Stratified Sampling19 RTL Faults and VLSI System Coverage n Experimental results demonstrate RTL fault coverage of a module to be a good statistical estimate of the gate-level fault coverage n A VLSI system consists of many interconnected modules n Overall RTL fault-list of a VLSI system does not constitute a representative sample of the gate-level fault-list

20. Sep. 26, 2001Agrawal: Stratified Sampling20 Error at System Level RTL Coverage = (0.91 x 100 + 0.39 x 100) / 200 = 65% Gate Coverage = (0.90 x 150 + 0.40 x 400) / 550 = 54% n A correct estimation of gate-level fault coverage from RTL coverage: 91 x (150 / 550) + 39 x (400 / 550) = 53% M2 100 faults 39% cov. M1 100 faults 91% cov. M1 150 faults 90% cov. M2 400 faults 40% cov. RTL Gate- level

21. Sep. 26, 2001Agrawal: Stratified Sampling21 Application of Stratified Sampling n Fault population of a VLSI system divided into strata according to RTL module boundaries n RTL faults in each module are considered a sample of corresponding gate-level faults n The stratified RTL coverage is an estimate of the gate-level coverage: W m = stratum weight of m th module = G m /G c m = RTL fault coverage of m th module G m = number of gate-level faults in m th module G = number of all gate-level faults in the system M = number of RTL modules in the system M C =    W m c m m=1

22. Sep. 26, 2001Agrawal: Stratified Sampling22 Application of Stratified Sampling Range of coverage, where, r m = number of RTL faults in m th module t = value from tables of normal distribution The technique requires knowledge of stratum weights and not absolute values of G m and G      c m (1  c m )  WmWm r m  1 m=1 M C + t 

23. Sep. 26, 2001Agrawal: Stratified Sampling23 Stratum Weight Extraction Techniques n Logic synthesis based weight extraction W m = G m /G n Floor-planning based weight extraction W m = A m /A n Entropy-measure based weight extraction

24. Sep. 26, 2001Agrawal: Stratified Sampling24 Experimental Procedure n Technology-dependent weight extraction Several unique gate-level netlists obtained by logic synthesis from the same RTL code Each synthesis run performed using a different set of constraints, e.g., area optimization (netlist 1), speed optimization (netlist 2), or combined area and speed optimizations (netlists 3 and 4) Strata weights calculated using gate-level fault lists of various synthesized netlists n Technology-independent weight extraction Stratum weights calculated using area distribution among modules n Each set of stratum weights used to calculate RTL fault coverage and error bounds n Impact of estimation error investigated

25. Sep. 26, 2001Agrawal: Stratified Sampling25 Experimental Data: Weight Distributions

26. Sep. 26, 2001Agrawal: Stratified Sampling26 Experimental Data: RTL Fault Coverage

27. Sep. 26, 2001Agrawal: Stratified Sampling27 Experimental Data: Error Bounds

28. Sep. 26, 2001Agrawal: Stratified Sampling28 Timing Controller ASIC (17,126 Gates)

29. Sep. 26, 2001Agrawal: Stratified Sampling29 A DSP ASIC (104,881 Gates)

30. Sep. 26, 2001Agrawal: Stratified Sampling30 Conclusion n Main ideas of RTL fault modeling A small or high-level RTL module contributes few RTL faults, but large statistical tolerance gives a correct coverage estimate Stratified sampling accounts for varying module sizes and for different RTL details that may be used Stratum weights appear to be insensitive to specific details of synthesis n Advantages of the proposed RTL fault model High-level test generation and evaluation Early identification of hard-to-test RTL architectures Potential for significantly reducing run-time penalty of the gate-level fault simulation

31. Sep. 26, 2001Agrawal: Stratified Sampling31 References n V. D. Agrawal, “Sampling Techniques for Determining Fault Coverage in LSI Circuits,” J. Digital Systems, vol. V, no. 3, pp. 189- 202, 1981. n V. D. Agrawal and H. Kato, “Fault Sampling Revisited,” IEEE Design & Test of Computers, vol. 7, no. 4, pp. 32-35, Aug. 1990. n P. A. Thaker, M. E. Zaghloul, and M. B. Amin, “Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementation,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 256-259. n P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, “Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test,” Proc. 17th IEEE VLSI Test Symp., Apr. 1999, pp. 182-188. n P. A. Thaker, Register-Transfer Level Fault Modeling and Evaluation Techniques, PhD Thesis, George Washington University, Washington, D.C., May 2000. n P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, “Register-Transfer Level Fault Modeling and Test Evaluation Techniques for VLSI Circuits,” Proc. Int. Test Conf., Oct. 2000, pp. 940-949. n This presentation is available from the website http://cm.bell- labs.com/cm/cs/who/va

32. Sep. 26, 2001Agrawal: Stratified Sampling32 Thank you