1. Logic Synthesis Outline –Logic Synthesis Problem –Logic Specification –Two-Level Logic Optimization Goal –Understand logic synthesis problem –Understand logic optimization problem From Hank Walker

2. Logic Synthesis Problem Map from logic equations to gate-level combinational logic –will consider FSM synthesis later Goals –maximize speed –minimize power –minimize chip/board area Constraints –target technology –CAD tool CPU time a’bc + abc + dbc + d b c d b c d

3. Logic Specification.i 3.o 3.p 4 10x101 x01100 110110 11x010.e Two-level logic equations –sum of products –“PLA format” –“ESPRESSO format” Multiple-level logic equations –Berkeley Logic Intermediate Format (BLIF) –arbitrary set of equations –generated in converting directly from RTL »e.g. logic equations for ALU –generated from gate-level netlist x = ab’ + b’c + abc’ y = abc’ + ab z = ab’ literaloperand x = abc’ + def + ghi + jkl +... y = bc + e’ + ghi + jk +... x = (a(b+c)d + ef(i+j))(k + l)

4. Logic Specification Logic equations are flattened to two levels –AND-OR, NAND-NAND, NOR-NOR –common starting point for most tools –eliminates any input bias –causes exponential explosion in equation size in worst case »does not occur in practice

5. Logic Synthesis Problem 1. logic equation simplification –reduce literal and operand count »less “stuff” to implement –generally reduces chip area –does not always minimize delay 2. logic synthesis –map equations to generic gates »AND, OR, NOT 3. gate-level optimization –“local” transformations for speed, area, power »e.g. AND-NOT => NAND –need estimate of technology costs 4. technology mapping –map from gates to component library »FPGAs, standard cells, TTL, etc.

6. Karnaugh Maps - Two-Level Minimization A B C D 00 0 1 0 00 110 111 101 F = A’BC’D + A’BCD + ABC’D’ + ABC’D + ABCD + ABCD’ + AB’C’D’ + AB’C’D F = AB + AC’ + BD Build map - 2 N entries –label entries »0 - F = 0 »1 - F = 1 »X - F = don’t care Find minimum prime cover –cover - set of terms whose union is true for all entries that are 1 »can also cover all 0 entries instead and complement F –prime - terms are simplest (largest cover) they can be »AB vs. ABC + ABC’ –minimum - fewest terms F’ = A’B’ + B’C + A’D’

7. Examples A B C D 00 0 1 0 00 110 111 101 F = AC’ + BD + ABCD’ ABCD’ is not prime A B C D 00 0 1 0 00 110 111 101 F = AC’ + BD F is not a cover

8. Examples A B C D 00 0 1 0 00 110 111 101 F’ = A’B’ + A’D’ + B’C A B C D 00 X 1 0 00 110 111 1X1 F = A + BD Use don’t care terms when determining if term is prime Solve for complement

9. Can Get Into Local Minima A B C D 11 0 1 1 11 001 001 000 A B C D 11 0 1 1 11 001 001 000 A B C 11 0 1 1 11 001 001 000 D A B C 11 0 1 1 11 001 001 000 D

10. Local Minima A B C 11 0 1 1 11 001 001 000 D A B C 11 0 1 1 11 001 001 000 D A B C 11 0 1 1 11 001 001 000 D A B C 11 0 1 1 11 001 001 000 D

11. A B C 11 0 1 1 11 001 001 000 D Result is not minimal A B C 11 0 1 1 11 001 001 000 D F = BD’ + A’D’ + A’B’F = A’B’ + BD’ Result is minimal Solution –try different cover sequences Minimum cover is NP-complete –exponential time in worst case Usually many minima

12. Problems with Karnaugh Maps Exponential space in number of inputs –e.g. 100 input function needs 2 100 cells –very inefficient if number of 1 or 0 cells is small Needs of two-level minimization –efficient data structure »ideally linear in size of function –efficient means of searching for minimal prime cover »get close to optimal in reasonable time –serve as a building-block for multi-level minimization

13. Logic Optimization Definitions N-dimensional boolean space - 2 N points, each associated with a unique set of N literals –e.g. entries in a Karnaugh map or truth table –each point is a minterm –e.g. abcd, ab’cd, in space cube - conjunction (AND) of literals in N-dim boolean space –points on N-dim hypercube that are 1 –examples: a’bc, acd expression - disjunction (OR) of cubes, i.e. equation –example: a’bc + def don’t cares - missing literals from cube –example: abc in space of, d is don’t care –result is cube covering larger part of space –abc = abcd’ + abcd a’b’ a’bab ab’ cube: a’ DC: b space:

14. Two-Level Logic Optimization Approach –find minimal set of cubes to cover ON-set (1 minterms) –each cube = AND gate »minimal cubes => minimal AND gates –each expression = cubes + OR gate »one expression (OR gate) per output –exploit don’t cares to increase cube sizes »each DC doubles cube size »cube must only cover 1 or DC vertices »or cover OFF-set (0 minterms) instead a’b’ a’bab ab’ a’ + b redundancy in cube cover ON DC OFF

15. Two-Level Logic Optimization Minimal set of cubes –minimum graph covering problem –NP-complete - exponential in worst case –must use heuristic search Complications –solve simultaneously for each expression (output) »minimize total number of unique cubes –consider ON vs. OFF vs. DON’T CARE set x = ab’ + b’c + abc’ y = abc’ + ab z = ab’.i 3.o 3.p 4 10x101 x01100 110110 11x010.e.i 3.o 3.p 4 -01 100 11- 010 1-0 100 10- 001.e x = b’c + ac’ y = ab z = ab’ ESPRESSO outputESPRESSO input

16. Two-Level Logic Optimization Approach –minimize cover of ON-set of function »ON-set is set of vertices for which expression is TRUE »minimum set of cubes –exploit don’t cares to increase cube sizes Algorithm –start with cubes covering the ON-set »this is just sum-of-products form –iteratively expand, shrink, add, remove cubes –remove redundant (covered) cubes –result is irredundant cover a’b’ a’bab ab’a’b’ a’bab ab’ x = a’b + ab + a’b’ x = a’ + b

17. ESPRESSO Algorithm Forig = ON-set; /* vertices with expression TRUE */ R = OFF-set; /* vertices with expression FALSE */ D = DC-set; /* vertices with expression DC */ F = expand(Forig, R); /* expand cubes against OFF-set */ F = irredundant(F, D); /* remove redundant cubes */ do { F = reduce(F, D); /* shrink cubes against ON-set */ F = expand(F, R); F = irredundant(F, D); } until cost is “stable”; /* perturb solution */ G = reduce_gasp(F, D); /* add cubes that can be reduced */ G = expand_gasp(G, R); /* expand cubes that cover another */ F = irredundant(F+G, D); } until time is up; ok = verify(F, Forig, D); /* check that result is correct */

18. Cube Operations Expand –expand essential cubes in F in decreasing size to a prime cube –prime cube - fully expanded against OFF-set –essential cube - contains essential vertex –essential vertex - minterm no other cube covers –remove any covered cubes 00 0111 10 00 0111 10 Expand ON DC OFF

19. Cube Operations 00 0111 10 Irredundant 00 0111 10 ON DC OFF Irredundant –find minimal cover with each cube containing an essential vertex –find relatively essential cubes E »removing them violates cover - keep them –redundant cubes R = F - E »can be individually removed »totally redundant R t - covered by E+D »remove R t »partially redundant R p - R - R t –new F = E + minimal set of R p E RpRp RpRp RtRt

20. Cube Operations 00 0111 1000 0111 10 Reduce ON DC OFF Reduce –shrink cubes in descending order of size while maintaining cover –smaller cubes can expand in more directions –smaller cubes more likely to be covered by other cubes during expansion

21. Cube Operations 00 0111 1000 0111 10 Expand Gasp 00 0111 10 Reduce Gasp 00 0111 10 ON DC OFF Reduce Gasp –for each cube add a subcube not covered by other cubes Expand Gasp –expand subcubes and add them if they cover another cube –later use Irredundant to discard redundant cubes –this is a “last gasp” heuristic for exploration »no ordering by cube size

22. Example a’b’ a’bab ab’a’b’ a’bab ab’ x = a’b + ab + a’b’ Expand a’b’ a’bab ab’ Irredundant a’b’ a’bab ab’ Reduce a’b’ a’bab ab’ Expand Irredundant a’b’ a’bab ab’ Cost Stable x = a’ + b

23. Examples Essential and Redundant Cubes Prime & Irredundant Cover RpRp RpRp E E Initial CoverReduceExpand in right direction

24. Conclusions Experimental Results –ESPRESSO algorithm gets minimum or close to minimum cover where cover is known –up to 10 000 input literals, 100 inputs, 100 outputs tested –CPU time < 12 min on high-speed workstation Application –PLA minimization –use as subroutine in multi-level logic minimization »minimize pieces of larger circuit