1. Network based System on Chip Part A Performed by: Medvedev Alexey Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006

2. Problem to solve In modern high-speed systems that contain a lot of components traffic is a major problem. Components are interacting with each other using a bus.

3. Problem

4. This architecture has certain disadvantages:  low speed,  allows to connect only two components at a given time,  no parallel access,  unconfigurable.

5. Solution

6. Network-on-Chip A network-like structure with central units on junctions which manage and direct the traffic  highly customizable  allows any number of parallel connections  maintains high throughput at all times  traffic control and routing mechanisms

7. Advanced features Service levels allow to give priorities to certain components Wormhole mechanism lowers the total propagation delay in the net Virtual channels prevent congestion in the network

8. General NoC Router Central NoC unit for directing data streams and traffic control n input ports (IP) n output ports (OP) m service levels (SL) per each port

9. Packet structure Each packet consists of flits which are the minimal data unit in the net Routers retransmit packets further flit by flit by reading and storing the destinations address of the packet from the first flit and assigning a buffer for that packet.

10. NoC Router Buffers Crossbar Controller Input Port Output Port Input Port Output Port Input Port

11. Input port Receives data from another router or module. Consists of control unit and CRT (Current Routing Table) to store routing addresses and a FIFO buffer for each service level.

12. Input port schematic FIFO CRT#1 Transfer Control CRT#0 DMXDMX data_in ftype, sl buffer_credits write_enable data_out 1 data_out 0 address 0 address 1

13. Input port schematic

14. CRT schematic

15. Output port Transmits data to another router or module. Consists of a single buffer for each service level and a mux to select current service level. Also, another mux is used to switch to idle state.

16. Output port DFF ‘0’ MUXMUX MUXMUX idle sl_select data_out data_in 1 data_in 0

17. Output port schematic

18. Crossbar Performs data routing between input and output ports in a router. Implemented using steering logic.

19. Crossbar MUXMUX MUXMUX MUXMUX MUXMUX OP0 level0 OP1 level0 OP0 level1 OP1 level1 IP0 level0 IP1 level0 IP0 level1 IP1 level1

20. Crossbar schematic

21. Crossbar controller Directs data streams in the crossbar. Uses round-robin scheduler and address data from IP’s CRT to determine data streams’ direction.

22. Crossbar controller schematic

23. Crossbar controller FSM One FSM for each OP and service level Transition to working states happens when there is waiting data on either IPs and the OP is able to receive data. Transition between working states happens when ‘end of packet’ flit received on one IP and there is waiting data on the other IP and the OP is able to receive flits. Transition to idle state happens when OP can’t receive data or when corresponding IP changed address or emptied its buffer.

24. Simulation results Max. clock frequency: 244 MHz In-out latency: 4 cc Port switch latency: 0 cc High to Low SL switch latency: 0 cc Low to High SL switch latency: 1 cc

25. Simulation 1: Latency In to out transition time Several separated packets transmitted from IP0 to OP2

26. latency packet1

27. Simulation 2: Service Levels Switching between service levels Low priority packet from IP0, high priority packet from IP2, to OP1 Transmission of low priority data is interrupted and high priority data transmission takes place

28. packet1 packet2

29. Simulation 3: Parallel transfer Two input ports transmit data simultaneously to two output ports Packet from IP0 to OP2, packet from IP2 to OP1

30. packet1 packet2

31. Simulation 4: Round- robin scheduling Two input ports transmit equally prioritized data to the same output port Packets from IP0 and IP2 to OP1 Both ports take turns to transmit data

32. packet1 packet2

33. Simulation 5: Buffer credits Buffer overflow on receiving side Router 1 transmits packets to IP0 of Router 2 with destination at OP2 of Router 2 while Router 2 transmits a very long packet from IP1 to OP2 When the buffer overflows, IP emits buffer_credit signal which stops transmission of the packet. After the buffer empties, transmission continues

34. packet1 packet2

35. Project status Implemented a 3x3 router which supports two service levels and built a simple NoC that allows data transfers between modules on the chip.

36. Future plan Implementing a Source Flow Control Unit Implementing a Hot-Spot Flow Control Unit (Scheduler) for bandwidth - consuming components. Evaluating Space-Cost efficiency of the design

37. Schedule Hardware router implementation – 1 wk Traffic generator and sink implementation – 1 wk Source and Hot-Spot control units implementation – 2-3 wk Building a real-life system based on NoC with Hot-Spot control units – 3 wk

38. The End