1. Energy Evaluation Methodology for Platform Based System-On- Chip Design Hildingsson, K.; Arslan, T.; Erdogan, A.T.; VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on 19-20 Feb. 2004 Page(s):61 - 68 Presenter : hyChen

2. Abstract This paper presents a methodology that speeds up the process of estimating the system level energy efficiency for synthesisable AMBA based SOC platforms that are scalable by means of integrating additional Intellectual Property (IP) hardware through the AMBA bus system. The methodology facilitates a modular approach where overall energy consumption is calculated based on Power Models that are developed for each defined sub-block (or Entity) of the platform. To automate the evaluation process we developed a tool – called PEX – that combines Power Models with utilisation statistics of the system Entities, and that provides a fast way of analysing tradeoffs for speed, energy and power consumption for various system configurations. Detailed results are presented for the analysis of two implementation scenarios of the Rijndael AES algorithm using the SPARC V8 compatible LEON architecture.

3. What ’ s the problem Power and energy are crucial performance metrics in SOC design, especially for handheld devices. A crucial trade-off in power modeling is that between speed and accuracy. Low-level : accurate but slow. High-level : faster but less accurate. a methodology for predicting the system-level energy-efficiency when integrating IP modules onto an existing synthesisable SOC platform, based around the AMBA bus standard

4. Platform Definition

5. Platform Definition (cont.) LEON microprocessor (IEEE-1754 standard) Multiplication, division and Multiply-And-Accumulate. Interface to FPU and CP. Harvard architecture. Extra local ram for performance critical code. AMBA 2.0 on-chip Bus Memory Controller Handles 8/16/32-bits wide buses for external memories. Additional IP Module

6. Entities Synopsys Design Compiler UMC.18 Not use the FPU or the CP Transistors counts from compiling the gate-level netlist in Synopsys Nanosim

7. Power Model-Processor entity(1) Energy cost per instruction instruction occupies the execution stage. Minimum and maximum bounds. Example : ld instruction Minimum: moving zero data from memory into a local register with zero value Maximum: moving 0x00000000 followed by 0xffffffff gate-level simulation in Modelsim. Sequences of instructions written in assembly.

8. Power Model-Processor entity(2)

9. Power Model-Memory entity data supplied by the silicon provider. Worst case power (1.8v) (  W/MHZ) Register (Dual-port SRAM) : 58.0 Cache module 4kb (SRAM) : 210 Cache tag memory module (SRAM) : 143 Main memory:only analysis event statistics. Additional entities (IP) on AMBA bus.

10. Events The instruction-set simulation : TSIM cycle count, program counter value, instruction code, operands. Events Execution time, CPI, instruction types. Data/Instruction cache utilisation. Data transfers to IP modules Memory-mapped IP

11. Example IP-AES Functionality of the AES module: 6 operating modes each for encryption and decryption and the idle mode.(13 modes) Three unique addresses: Write to input select register. Write to input data register. Read from output. 16 byte for plaintext data, and 16,24,32 bytes for key data.

12. AES-power consumption 51 test case.

13. AES-power consumption (cont.)

14. PEX PEX (Power EXtractor) is the power and energy analysis tool. Input : TSIM trace data and entity power model Power consumption: Processor Memory Addition IP module

15. PEX-processor M is the number of instruction types in trace. P instr(i) : power cost. N instr(i) : number of execution cycle (type i). N tot : total number of execution cycle. K : the instruction overhead effects for min and max conditions.

16. PEX-other Memory Average power consumption is calculated for the appropriate clock frequency. Main memory: Access Index = total number of bits when memory accesses. Addition IP The same as processor.

17. Result analysis SW vs. HW/SW

18. Result analysis (cont.)

20. Verification Gate-level Simulation: processor + AES IP+ AMBA

21. Verification (cont.) Synopsys Power Compiler vs. Nanosim Gate-level vs. transistor-level Nanosim are more time consuming. Range from 13.5% - 22.8%

22. Conclusion A methodology capable of evaluating crucial tradeoffs (energy, power). System-level : AMBA-base SOC platform Accuracy : Determine the choice of tool to use for building the power models. Speed-up: Evaluating the energy-efficiency. Events collected from instruction-set simulator. Power models for hardware entities is a one time effort.