1. Task-Switching How the x86 processor assists with context-switching among multiple program-threads

2. Program Model Programs consist of data and instructions Data consists of constants and variables, which may be ‘persistent’ or ‘transient’ Instructions may be ‘private’ or ‘shared’ These observations lead to a conceptual model for the management of programs, and to special processor capabilities that assist in supporting that conceptual model

3. Conceptual Program-Model TEXT DATA BSS STACK heap runtime library Private Instructions (persistent ) Initialized Data (persistent) Uninitialized Data (persistent) Private Data (transient) Shared Instructions and Data (persistent) created at compile time created during runtime

4. Task Isolation The CPU is designed to assist the system software in isolating the private portions of one program from those of another while they both are residing in physical memory, while allowing them also to share certain instructions and data in a controlled way This ‘sharing’ includes access to the CPU, whereby the tasks take turns at executing

5. Multi-tasking TEXT DATA BSS heap STACK TEXT DATA BSS heap STACK shared runtime library user-space (ring3) supervisor-space (ring0) TSS 1TSS 2 Task #1 Task #2 GDTIDT IDTR GDTR CS DS SS SP IP TR

6. Context-Switching The CPU can perform a ‘context-switch’ to save the current values of all its registers (in the memory-area referenced by the TR register), and to load new values into all its registers (from the memory-area specified a new Task-State Segment selector) There are four ways to trigger this ‘switch’ operation on x86 processors

7. How to cause a task-switch? Use a ‘jmpf’ instruction (far jump): jmpf #0, #task_selector Use a ‘callf’ instruction (far call): callf #0, #task_selector Use an ‘int-n’ instruction (with a task-gate): int 0x80 Use an ‘iret’ instruction (with NT=1): iret

8. ‘jmpf’ and ‘callf’ These instructions are similar – they both make use of a ‘selector’ for a Task-State Segment descriptor Base[ 15..0 ]Limit[ 15..0 ] Base[31..24] DPLDPL Base[23..16]type0P TSS Descriptor-Format type: 16bitTSS( 0x1=available or 0x3=busy) or 32bitTSS( 0x9=available or 0xB=busy)

9. When to use ‘jmpf’ or ‘callf’? Use ‘jmpf’ to switch to a different task in case you have no intention of returning Use ‘callf’ to switch to a different task in case you want to ‘return’ to this task later

10. No Task Reentrancy! Since each task has just one ‘save area’ (in its TSS), it must not be possible for a task to be recursively reentered! The CPU enforces this prohibition using a ‘busy’ bit within each task’s TSS descriptor Whenever the TR register is loaded with a new selector-value, the CPU checks to be sure the task isn’t already ‘busy’; if it’s not, the task is entered, but gets marked ‘busy’

11. Task-Nesting But it’s OK for one task to be nested within another, and another, and another… TSS #4 TR LINK TSS #3 LINK TSS #2 LINK TSS #1 LINK callf current TSS

12. The NT-bit in FLAGS When the CPU switches to a new task via a ‘callf’ instruction, it sets NT=1 in FLAGS (and leaves the old TSS marked ‘busy’) The new task can then ‘return’ to the old task by executing an ‘iret’ instruction (the old task is still ‘busy’, so returning to it with a ‘callf’ or a ‘jmpf’ wouldn’t be possible)

13. Task-switch Semantics Fieldjmp effectcallf effectiret effect new busy-bitchanges to 1 changes to 1 stays = 1 old busy-bitis clearedstays = 1is cleared new NT-flagIs clearedIs set to 1no change old NT-flagno change is cleared new LINK-fieldno changenew valueno change old LINK-fieldno change

14. Task-Gate Descriptor It is also possible to trigger a task-switch with a software or hardware interrupt, by using a Task-Gate Descriptor in the IDT Task-State Segment Selector DPLDPL P type (=0x5) 0 Task-Gate Descriptor Format

15. ‘Threads’ versus ‘Tasks’ In some advanced applications, a task can consist of multiple execution-threads Like tasks, threads take turns executing (and thus require ‘context-switching’) CPU doesn’t distinguish between ‘threads’ and ‘tasks’ – context-switching semantics are the same for both Difference lies in ‘sharing’ of data/code

16. A task with multiple threads CODE 1CODE 2 DATA 1 STACK 1STACK 2 heap TEXT (some shared, some private) DATA (some shared, some private) STACKS (each is thread-private) DATA 2 user-space (ring3) supervisor-space (ring0) TSS 1TSS 2 Each thread has its own TSS-segment

17. Demo program: ‘twotasks.s’ We have constructed a simple demo that illustrates the CPU task-switching ability It’s one program, but with two threads Everything is in one physical segment, but the segment-descriptors create a number of different ‘logical’ segments One task is the ‘supervisor’ thread: it ‘calls’ a ‘subordinate’ thread (to print a message)

18. Thread #2 uses an LDT To support isolation of memory-segments among distinct tasks or threads, the CPU allows use of ‘private’ descriptor-tables Same format for the segment-descriptors But selectors use a Table-Indicator bit Descriptor-table index fieldRPL TITI 3 2 1 015 Format of a segment-selector (16-bits) TI = Table-Indicator (0 = GDT, 1 = LDT) RPL = Requested Privilege-Level

19. In-class Exercise #1 In our ‘twotasks.s’ demo, the two threads will both execute at privilege-level zero An improved version of this demo would have the ‘supervisor’ (Thread #1) execute in ring 0 and the ‘subordinate’ (Thread #2) execute in ring 3 Modify this demo-program, to incorporate that suggested improvement!

20. More enhancements? The demo-program could be made much more interesting if it used more than one subordinate thread, and if the supervisor thread took turns repeatedly making calls to each subordinate (i.e., time-sharing) You can arrange for a thread to be called more than once by using a ‘jmp’ after the ‘iret’ instruction (to re-execute the thread)

21. In-class Exercise #2 Modify the demo so it has two subordinate threads, each of which prints a message, and each of which can be called again and again (i.e., add a jmp-instruction after iret): begin:; entry-point to the thread... iret jmp begin